Intel Xeon Processor MP Specification Update

26 Intel
®
Xeon
®
Processor MP Specification Update
Errata
Status: For the steppings effected, see the Summary Table of Changes.
O19 PAT index MSB may be calculated incorrectly
Problem: When Mode C or Mode B paging support is enabled and all of the following events occur:
• A page walk returns the page directory entry (PDE) for a large page from memory.
• A subsequent page walk returns the page table entry (PTE) for a 4k page from memory and the
page attribute table (PAT) upper index bit (bit 7) in this PTE is set to 1b.
It is possible that the PAT upper index bit in the PTE is incorrectly ignored and assumed to be 0b.
The result is that the memory type in the PAT that should have come from the corresponding PAT
index [4-7] incorrectly comes from PAT index [0-3].
Implication: If an operating system has programmed the PAT in an asymmetrical fashion i.e., PAT[0-3] is
different from PAT[4-7] then an incorrect memory type may be used.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O20 System bus interrupt messages without data which receive a hardfailure
response may hang the processor
Problem: When a system bus agent (processor or chipset) issues an interrupt transaction without data onto
the system bus and the transaction receives a HardFailure response, a potential processor hang can
occur. The processor, which generates an inter-processor interrupt (IPI) that receives the
HardFailure response, will still log the MCA error event cause as HardFailure, even if the APIC
causes a hang. Other processors, which are true targets of the IPI, will also hang on
hardfail-without-data, but will not record an MCA HardFailure event as the cause. If a HardFailure
response occurs on a system bus interrupt message with data, the APIC will complete the operation
so as not to hang the processor.
Implication: The processor may hang.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Tables of Changes.
O21 Bus invalidate line requests that return unexpected data may result in L1
cache corruption
Problem: When a bus invalidate line (BIL) request receives unexpected data from a deferred reply, and a
store operation write combines to the same address, there is a small window where the L1cache is
corrupt, and loads can retire with this corrupted data. This erratum occurs in the following
scenario:
• A RFO transaction is issued by the processor and hits a line in shared state in the L2 cache.
• The RFO is then issued on the system bus as a 0 length read-invalidate (BIL), since it doesn't
need data, just ownership of the cache line.
• This transaction is deferred by the chipset.
• At some later point, the chipset sends a deferred reply for this transaction with an implicit
write-back response. For this erratum to occur, no snoop of this cache line can be issued
between the BIL and the deferred reply.
• The processor issues a write-combining store to the same cache line while data is returning to
the processor. This store straddles an 8-byte boundary.
• Due to an internal boundary condition, a time window exists where the L1 cache contains
corrupt data which could be accessed by a load.