Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Memory Interface Routing Guidelines
90 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
Figure 6-8. Trace Width/Spacing for CMDCLK/CMDCLK# Routing
Core 5.2 mil
Dielectric 9.6 mil
2.1 mil (1 oz + plating)
Power
Dielectric
Power
Dielectric
Ground
Main Core
Dielectric
Core
Ground
Dielectric
Core
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
2.1 mil (1 oz + plating)
Core 5.2 mil
Dielectric 4.3 mil
Core 14.0 mil
Dielectric 9.6 mil
Dielectric 4.3 mil
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
CMDCLK CMDCLK#
CMDCLK#CMDCLK
CMDCLK CMDCLK#
CMDCLK
Trace
Width
CMDCLK#
Differential
Spacing
Signal
Signal
Signal
Signal
Group
Spacing
Trace
Width
Trace
Width