Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

VTT_DDR
R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
VTT_DDR
VTT_DDR
VTT_DDR
VTT_DDR
+ +
E7500: Rt = 33 ohms
E7501: Rt = 39.2 ohms
Two Caps for each R-Pak
Two Caps for each R-Pak
DDR Channel A Termination
Two Caps for each R-Pak
Pull up should be within
E7501: NOPOP
E7500: 0 ohm
E7501: 49.9 ohms
E7500: 47 ohms
1" of DDRA_RCV_EN_IN
RCV_EN loop should be 15 inches
total route from MCH back to MCH.
19 85
DDRA_RCV_EN_OUT
12
R223
49.9
1%
R224
0
NOPOP
1 2 3 45
6 7 8
RP235
39.2
1%
1 2 3 45
6 7 8
RP234
39.2
1%
1 2 3 4 5
6 7 8
RP233 39.2
1%
1 2 3 45
6 7 8
RP232
39.2
1%
1 2 3 4 5
6 7 8
RP231 39.2
1%
1 2 3 45
6 7 8
RP230
39.2
1%
1 2 3 45
6 7 8
RP229
39.2
1%
1 2 3 4 5
6 7 8
RP228 39.2
1%
1 2 3 45
6 7 8
RP227
39.2
1%
1 2 3 4 5
6 7 8
RP226 39.2
1%
1 2 3 4 5
6 7 8
RP225
39.2
1%
1 2 3 45
6 7 8
RP224
39.2
1%
1 2 3 4 5
6 7 8
RP223
39.2
1%
1 2 3 45
6 7 8
RP222
39.2
1%
1 2 3 4 5
6 7 8
RP221
39.2
1%
1 2 3 45
6 7 8
RP220
39.2
1%
1 2 3 4 5
6 7 8
RP219
39.2
1%
1 2 3 45
6 7 8
RP218
39.2
1%
1 2 3 45
6 7 8
RP242
39.2
1%
3 45
6 7 8 1
2
1%
39.2
RP241
1 2 3 45
6 7 8
RP240
39.2
1%
1 2 3 45
6 7 8
RP239
39.2
1%
1 2 3 4 5
6 7 8
RP238 39.2
1%
1 2 3 4 5
6 7 8
RP237
39.2
1%
1 2 3 4 5
6 7 8
RP236 39.2
1%
1 2 3 4 5
6 7 8
RP213 39.2
1%
1 2 3 4 5
6 7 8
RP214
39.2
1%
1 2 3 4 5
6 7 8
RP215
39.2
1%
DDRB_CKE0
13,21,22,23
1 2 3 45
6 7 8
RP216
39.2
1%
1 2 3 4 5
6 7 8
RP217 39.2
1%
12,16
DDRA_CS0_N_R
12,16
DDRA_CS1_N_R DDRB_CS0_N_R
13,21
DDRB_CS1_N_R
13,21
DDRA_CS5_N_R
12,18
DDRA_CS4_N_R
12,18
20,21,22,23
DDRB_DQS12_R
20,21,22,23
DDRB_DQ29_R
12,16,17,18
DDRA_MA5_R
20,21,22,23
DDRB_DQ23_R
15,16,17,18
DDRA_DQ25_R
15,16,17,18
DDRA_DQS3_R DDRA_DQ46_R
15,16,17,18
DDRA_DQ42_R
15,16,17,18
DDRA_DQS5_R
15,16,17,18
DDRA_DQ57_R
15,16,17,18
DDRA_DQ56_R
15,16,17,18
DDRA_DQ61_R
15,16,17,18
DDRA_DQ60_R
15,16,17,18
DDRA_CB6_R
15,16,17,18
DDRA_CB2_R
15,16,17,18
DDRA_DQS17_R
15,16,17,18
DDRA_DQS8_R
15,16,17,18
12,16,17,18
DDRA_CAS_N_R DDRA_DQ35_R
15,16,17,18
DDRB_RAS_N_R
13,21,22,23
DDRA_WE_N_R
12,16,17,18 12,16,17,18
DDRA_MA9_R
12,16,17,18
DDRA_MA7_R
12,16,17,18
DDRA_MA8_R
15,16,17,18
DDRA_DQS12_R
15,16,17,18
DDRA_DQ29_R
15,16,17,18
DDRA_DQ28_R
15,16,17,18
DDRA_DQ24_R DDRB_DQ30_R
20,21,22,23 15,16,17,18
DDRA_CB4_R
15,16,17,18
DDRA_DQ27_R DDRA_DQ36_R
15,16,17,18 15,16,17,18
DDRA_DQ32_R
15,16,17,18
DDRA_CB3_R
12,16,17,18
DDRA_MA0_R
13,21,22,23
DDRB_MA10_R DDRA_MA10_R
12,16,17,18
15,16,17,18
DDRA_CB0_R
20,21,22,23
DDRB_DQ31_R DDRA_MA1_R
12,16,17,18
15,16,17,18
DDRA_DQ59_R
15,16,17,18
DDRA_DQ63_R
15,16,17,18
DDRA_DQS16_R
15,16,17,18
DDRA_DQ62_R
15,16,17,18
DDRA_DQS7_R DDRA_DQ58_R
15,16,17,18
15,16,17,18
DDRA_DQ51_R
15,16,17,18
DDRA_DQ50_R
15,16,17,18
DDRA_DQ55_R DDRA_DQ54_R
15,16,17,18 15,16,17,18
DDRA_DQ49_R
15,16,17,18
DDRA_DQ53_R
15,16,17,18
DDRA_DQS15_R DDRA_DQS6_R
15,16,17,18 15,16,17,18
DDRA_DQ43_R
15,16,17,18
DDRA_DQ47_R
15,16,17,18
DDRA_DQ48_R DDRA_DQ52_R
15,16,17,18 15,16,17,18
DDRA_DQS14_R
15,16,17,18
DDRA_DQ41_R
15,16,17,18
DDRA_DQ45_R
15,16,17,18
DDRA_DQS4_R
15,16,17,18
DDRA_DQS13_R
15,16,17,18
DDRA_DQ39_R
15,16,17,18
DDRA_DQ38_R DDRA_MA4_R
12,16,17,18 12,16,17,18
DDRA_MA3_R
15,16,17,18
DDRA_DQ30_R DDRA_DQ31_R
15,16,17,18 12,16,17,18
DDRA_MA6_R
15,16,17,18
DDRA_DQ19_R DDRA_DQ23_R
15,16,17,18
15,16,17,18
DDRA_DQ22_R
12,16,17,18
DDRA_MA12_R DDRA_DQS2_R
15,16,17,18 15,16,17,18
DDRA_DQS11_R
12,16,17,18
DDRA_MA11_R
15,16,17,18
DDRA_DQ17_R
15,16,17,18
DDRA_DQ16_R DDRA_DQ21_R15,16,17,18
15,16,17,18
DDRA_DQ20_R DDRA_DQ11_R
15,16,17,18 15,16,17,18
DDRA_DQ13_R
15,16,17,18
DDRA_DQS1_R
15,16,17,18
DDRA_DQ12_R DDRA_DQ2_R15,16,17,18
15,16,17,18
DDRA_DQ5_R
15,16,17,18
DDRA_DQS9_R
15,16,17,18
DDRA_DQS0_R DDRA_DQ6_R15,16,17,18
0.1UF
C970
0.1UF
C971
0.1UF
C972
0.1UF
C973
0.1UF
C974
0.1UF
C975
0.1UF
C976
0.1UF
C977 C978
0.1UF 0.1UF
C979
0.1UF
C969
0.1UF
C968
0.1UF
C967
0.1UF
C966
0.1UF
C965
0.1UF
C964
0.1UF
C963
0.1UF
C962
0.1UF
C961
0.1UF
C960
0.1UF
C959
0.1UF
C958
0.1UF
C957
0.1UF
C956
21
100UF
C1568
1 2
C1567
100UF
0.1UF
C955
0.1UF
C954
0.1UF
C953
0.1UF
C952
0.1UF
C951
0.1UF
C950
0.1UF
C949
0.1UF
C948
0.1UF
C947
0.1UF
C946
0.1UF
C945
0.1UF
C944
0.1UF
C943
0.1UF
C942
0.1UF
C941
0.1UF
C940
0.1UF
C939
0.1UF
C938
0.1UF
C937
0.1UF
C936
0.1UF
C935
0.1UF
C934
0.1UF
C933
0.1UF
C932
0.1UF
C931
0.1UF
C930
0.1UF
C929
0.1UF
C928
0.1UF
C927 C926
0.1UF 0.1UF
C925
0.1UF
C924
0.1UF
C923
0.1UF
C922 C921
0.1UF 0.1UF
C980
DDRA_RCV_EN_IN
12
DDRA_CB7_R
15,16,17,18
15,16,17,18
DDRA_CB5_R
15,16,17,18
DDRA_DQ18_R
DDRA_DQ40_R
15,16,17,18 15,16,17,18
DDRA_DQ34_R
12,16,17,18
DDRA_MA2_R
15,16,17,18
DDRA_DQ26_R
12,16,17,18
DDRA_CKE0 DDRA_DQ44_R
15,16,17,18
DDRA_BA0_R
12,16,17,18
INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD 1.0
11/18/02
15,16,17,18
DDRA_DQ33_R
15,16,17,18
DDRA_CB1_R
DDRA_RAS_N_R
12,16,17,18
DDRA_DQ37_R
15,16,17,18
DDRA_DQ10_R
15,16,17,18
DDRA_DQ15_R
15,16,17,18
DDRA_DQ14_R
15,16,17,18
DDRA_DQS10_R
15,16,17,18