Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

+VCC_CPU +VCC_CPU
+VCC_CPU+VCC_CPU
+VCC_CPU
+VCC_CPU
+VCC_CPU
R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1 P2
ITP32B TAP
1-2 = P0 Only
2-3 = P0 + P1
TDO
TDI
TDO
TDI
P1
Debug
Port
TDI
TDO
P0
JP3
ITP USE DIAGRAM
Place these resistors
near J18 (Processor 0)
Place these termination
resistors at the ends of the traces.
VREF circuits for GTL+
ITP
9 85
24
22
20
18
16
14
12
10
8
6
4
25
23
21
19
17
15
13
11
9
7
5
3
1 2
J13
NO POP
51
R1092
INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD 1.0
11/18/02
ITP_TMS_P
4,6
4
ITP_TDO_P1
STPPWR
39.2
R1097
1%
R1090
1%
751.5K
1%
R1089
51
R1095
R1094
51
CPU_BPM3_N
4,6
R1096
51
CPU_BPM2_N
4,6
CPU_BPM4_N
4,6
4,6
CPU_BPM1_N
4,6
CPU_BPM0_N
CPU_BPM5_N
4,6
ITP_CPURST_N
10
84.5
1%
R114 R116
1%
84.5
R112
1%
84.5 84.5
1%
R109
2
3
1
JP26
R1120
200
ICH3_SMI_N
4,6,61
R118
200
ICH3_A20M_N
4,6,61
ICH3_IGNNE_N
4,6,61
4,6,61
CPU_LINT1_NMI
4,6,61
CPU_STPCLK_N
ICH3_INIT_N
4,6,61,68
R125
200
0
R107
R108
00
R111
R138
0
C89
1UF1UF
C90 C87 1UF 1UF
C88
200
R128
R127 200
200
R124 R123
200 200
R122
R110
1%
49.9
CPU1_GTL_VREF2
4
CPU0_GTL_VREF1 6 CPU0_GTL_VREF2
6
CPU1_GTL_VREF1 4
49.9
1%
R113R115
1% 49.9 49.9 1%
R117
ICH3_LINT0_INTR
4,6,61
ICH3_CPUSLP_N
4,6,61
R1098
51
R1093
51
51
R1091
27.4 1%
R1088
ITP_TDI_P1
4
6
ITP_TDO_P0
ITP_TDI_P0
6
DBR_RESET_N
79
ITP_TRST_N
4,6
ITP_TCK_P
4,6,9
ITP_TCK_P
4,6,9
ITP_BCLK1
80
ITP_BCLK0
80