Intel Xeon Processor 2.80 GHz Specification Update

28 Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update
Errata
that vector the system will GP fault. If the ISR does not do an end of interrupt (EOI) the bit for the
vector will be left set in the in-service register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector
was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts
that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore
the spurious vector should not be used when writing the LVT.
Status: For the steppings affected, see the Summary Table of Changes.
D53 The processor may issue multiple code fetches to the same cache line for
systems with slow memory
Problem: Systems with long latencies on returning code fetch data from memory, e.g. BIOS ROM, may
cause the processor to issue multiple fetches to the same cache line, once per each instruction
executed.
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this
erratum, in a commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D54 IRET under certain conditions may cause an unexpected Alignment Check
Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction
even though alignment checks were disabled at the start of the IRET. This can only occur if the
IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not
affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the
interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary
before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment
checks are disabled at the start of the IRET. This erratum can only be observed with a software
generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Table of Changes.
D55. Using 2M/4M pages when A20M# is asserted may result in incorrect address
translations.
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates
real-address mode address wraparound at 1 megabyte. However, if all of the following conditions
are met, address bit 20 may not be masked:
• Paging is enabled.
• A linear address has bit 20 set.
• The address references a large page.
• A20M# is enabled.
Implication: When A20M# is enabled and an address references a large page the resulting translated physical
address may be incorrect. This erratum has not been observed with any commercially available
operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit 20 could be
applied to an address that references a large page. A20M# is normally only used with the first
megabyte of memory.