64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 37
Errata
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this
erratum, in a commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J72. IRET under certain conditions may cause an unexpected alignment check
exception
Problem: In IA-32e mode, it is possible to get an alignment check exception (#AC) on the IRET instruction
even though alignment checks were disabled at the start of the IRET. This can only occur if the
IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not
affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the
interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary
before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment
checks are disabled at the start of the IRET. This erratum can only be observed with a software
generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Table of Changes.
J73. Using 2M/4M pages when A20M# is asserted may result in incorrect address
translations.
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates
real-address mode address wraparound at 1 megabyte. However, if all of the following conditions
are met, address bit 20 may not be masked:
• Paging is enabled.
• A linear address has bit 20 set.
• The address references a large page.
• A20M# is enabled.
Implication: When A20M# is enabled and an address references a large page the resulting translated physical
address may be incorrect. This erratum has not been observed with any commercially available
operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit 20 could be
applied to an address that references a large page. A20M# is normally only used with the first
megabyte of memory.
Status: No Fix
J74. Writing shared unaligned data that crosses a cache line without proper
semaphores or barriers may expose a memory ordering issue.
Problem: Software which is written so that multiple agents can modify the same shared unaligned memory
location at the same time may experience a memory ordering issue if multiple loads access this
shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans
a cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with
any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying shared data by
multiple agents: