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64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

ManualsBrandsIntel ManualsOtherIntel Xeon Processor 1.50 GHz, 1M Cache, 400 MHz FSB
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64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 39
Errata
J78. The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow Bit is not set when
Multiple Un-correctable Machine Check Errors occur at the same time
Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the same
internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS /
IA32_MC1_STATUS register, but the overflow bit may not be set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit in the
IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set
Workaround: None identified.
Status: No Fix.
J79. Debug Status Register (DR6) Breakpoint Condition Detected Flags May be
Set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under
certain boundary conditions when either:
• A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger
breakpoint instruction, or
• Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect
exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround: None identified.
Status: No Fix.
J80. A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E
or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in
PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a
PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an
entry is ignored and no page fault will occur due to its being set.
Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved
bits are set in paging-structure entries.
Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to “1”.
Status: No Fix.