64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

30 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
Status: For the steppings affected, see the Summary Table of Changes.
U52 With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP
Exception may tank single step trap before retirement of instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF = 1, it is possible for
external events to occur, including a transition to a lower power state. When resuming from a lower
power state, it may be possible to take the single step trap before the execution of the original FP
instruction completes.
Implication: When this erratum occurs, a single step trap will be taken unexpectedly.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U53 PDE/PTE loads and continuous locked updates to the same cache line may
cause system livelock
Problem: In a multi-processor configuration, if one processor is continuously doing locked updates to a
cache line that is being accessed by another processor doing a page table walk, the page table walk
may not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U54 Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may
update memory outside the BTS/PEBS buffer
Problem: If the BTS/PEBS buffer is defined such that:
1. The difference between the BTS/PEBS buffer base and the BTS/PEBS absolute maximum is
not an integer multiple of the corresponding record sizes,
2. The BTS/PEBS absolute maximum is less than a record size from the end of the virtual
address space, and
3. The record that would cross the BTS/PEBS absolute maximum will also continue past the end
of the virtual address space,
a. BTS/PEBS record can be written that will wrap at the 4-Gbyte boundary (IA-32) or 2^64
boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer.
Implication: Software that uses BTS/PEBS near the 4-Gbyte boundary (IA-32) or 2^64 boundary (Intel EM64T
mode), and defines the buffer such that it does not hold an integer multiple of records, can update
memory outside the BTS/PEBS buffer.
Workaround: Define the BTS/PEBS buffer such that the BTS/PEBS absolute maximum minus the BTS/PEBS
buffer base is an integer multiple of the corresponding record sizes as recommended in the IA-32
Intel
®
Architecture Software Developer's Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
U55 The base of an Local Descriptor Table (LDT) register may be non-zero on a
processor supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be nonzero.