Intel Xeon Processor Specification Update

Intel
®
Xeon
®
Processor Specification Update 47
Errata
P70 Incorrect duty cycle is chosen when On-Demand Clock Modulation is
enabled in a processor supporting Hyper-Threading Technology
Problem: When a processor supporting HT Technology enables On-Demand Clock modulation on both
logical processors, the processor is expected to select the lowest duty cycle of the two potentially
different values. When one logical processor enters the AUTOHALT state, the duty cycle
implemented should be unaffected by the halted logical processor. Due to this erratum, the duty
cycle is incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock modulation is
enabled on both logical processors.
Workaround: None at this time.
Status: For the steppings affected, see the Summary of Table of Changes.
P71 Memory aliasing of pages as uncacheable memory type and write back
(WB) may hang the system
Problem: When a page is being accessed as either UC or WC and WB, under certain bus and memory timing
conditions, the system may loop in a continual sequence of UC fetch, implicit WB, and Request
For Ownership (RFO) retries.
Implication: This erratum has not been observed in any commercially available operating system or application.
The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as
being unsupported in the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3,
Section 10.12.4 However, if this erratum occurs the system may hang.
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status: For the steppings affected, see the Summary of Table of Changes.
P72 A timing marginality in the Instruction Decoder unit may cause an
unpredictable application behavior and/or system hang
Problem: A timing marginality may exist in the clocking of the instruction decoder unit which leads to a
circuit slowdown in the read path from the Instruction Decode PLA circuit. This timing marginality
may not be visible for some period of time.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in an
unpredictable application behavior and/or system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. BIOS must load the microcode
update during the BIOS POST time prior to memory initialization.
Status: For the steppings affected, see the Summary of Table of Changes.
P73 Missing Stop Grant Acknowledge special bus cycle may cause a system
hang
Problem: If a Stop Grant Acknowledge special bus cycle is deferred by the processor for a period of time
long enough for the chipset to de-assert and then re-assert STPCLK# signal, a processor supporting
HT Technology may fail to detect the de-assertion and re-assertion of STPCLK# signal. When this
occurs, the processor will not issue a Stop Grant Acknowledge special bus cycle in response to the
second STPCLK# assertion.
Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.