Intel Xeon Processor Specification Update

28 Intel
®
Xeon
®
Processor Specification Update
Errata
P5 Processor may hang due to speculative page walks to nonexistent system
memory
Problem: A load operation issued speculatively by the processor that misses the data translation lookaside
buffer (DTLB) results in a page walk. A branch instruction older than the load retires so that this
load operation is now in the mispredicted branch path. Due to an internal boundary condition, in
some instances the load is not canceled before the page walk is issued.
The page miss handler (PMH) starts a speculative page walk for the load and issues a cacheable
load of the page directory entry (PDE). This PDE load returns data that points to a page table entry
in uncacheable (UC) memory. The PMH issues the PTE Load to UC space, which is issued on the
front side bus. No response comes back for this load PTE operation since the address is pointing to
system memory, which does not exist.
This load to non-existent system memory causes the processor to hang because other bus requests
are queued up behind this UC PTE load, which never gets a response. If the load was accessing
valid system memory, the speculative page-walk would successfully complete and the processor
would continue to make forward progress.
Implication: Processor may hang due to speculative page walks to non-existent system memory.
Workaround: Page directories and page tables in UC memory space must point to system memory that exists.
Status: For the steppings affected, see the Summary Table of Changes.
P6 Writing a performance counter may result in an incorrect counter value
Problem: Accessing a performance counter also enables the counter input so that writing one half of the
counter can cause the other half to increment. When a performance counter is written and the event
counter for the event being monitored is non-zero, the performance counter will be incremented by
the value on that event counter. Because the upper eight bits of the performance counter are not
written at the same time as the lower 32 bits, the increment due to the non-zero event counter may
cause a carry to the upper bits such that the performance counter contains a value higher than what
was written. The worst-case error caused by this can be about 4 billion counts.
Implication: When this erratum occurs, the performance counter will contain a different value from that which
was written.
Workaround: If the performance counter is set to select a null event and the counter configuration control register
(CCCR) for that counter has its compare bit set to zero, before the performance counter is written,
this erratum will not occur.
Status: For the steppings affected, see the Summary Table of Changes.
P7 Performance counter may contain incorrect value after being stopped
Problem: If a performance counter is stopped on the precise internal clock cycle where the intermediate carry
from the lower 32 bits of the counter to the upper eight bits occurs, the intermediate carry is lost.
Implication: When this erratum occurs the performance counter may contain a value about 4 billion (
2
32) less
than it should.
Workaround: Since this erratum does not occur if the performance counters are read when running, a possible
workaround is to read the counter before stopping it.
Status: For the steppings affected, see the Summary Table of Changes.
P8 REP MOV instruction with overlapping source and destination may result in
data corruption
Problem: When fast strings are enabled and a REP MOV instruction is used to move a string and the source
and destination strings overlap by 56 bytes or less, data corruption may occur.