Intel Xeon Processor LV and ULV Specification Update

Errata
20 Specification Update
AF7. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is UC,
the consolidated memory type may be treated as UC (rather than WC as specified in
IA-32 Intel
®
Architecture Software Developer's Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AF8. FPU Operand Pointer May Not be Cleared Following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87
FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector
(both fields form the FPUDataPointer). Saving the floating point environment with
FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an
intervening FP instruction may save uninitialized values for the FPUDataPointer
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point
image or floating point environment structure may appear to be random values.
Executing any non-control FP instruction with memory operand will initialize the
FPUDataPointer. Intel has not observed this erratum with any commercially available
software.
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or
floating point environment saved memory image to be correct, until at least one non-
control FP instruction with a memory operand has been executed.
Status: For the steppings affected, see the Summary Tables of Changes.
AF9. LTR Instruction May Result in Unexpected Behavior
Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an
unexpected behavior if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
Implication: If all conditions have been met then under certain circumstances LTR instruction may
result in system hang, memory corruption or other unexpected behavior. This
erratum has not been observed in commercial operating systems or software.
Workaround: Operating system software should align GDT to 8-bytes, as recommended in the
Software Developer‘s Manual section ―Segment Descriptor Tables‖. For performance
reasons, GDT is typically aligned to 8-bytes.
Status: For the steppings affected, see the Summary Tables of Changes.