Dual-Core Intel Xeon Processor 2.80 GHz Specification Update

10 Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update
Summary Tables of Changes
U = 64-bit Intel
®
Xeon
®
processor MP with up to 8 MB L3 cache
V = Mobile Intel
®
Celeron
®
processor on .13 Micron Process in Micro-FCPGA Package
W= Intel
®
Celeron
®
M processor
X=Intel
®
Pentium
®
M processor on 90nm process with 2-MB L2 Cache
Y=Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AA= Intel
®
Pentium
®
processor Extreme Edition and Intel
®
Pentium
®
D processor on 65nm
process
AB = Intel
®
Pentium
®
4 processor on 65 nm process
AC = Intel
®
Celeron
®
processor in 478-pin package
AD= Intel
®
Celeron
®
D processor on 65nm process
AE = Intel
®
Core
TM
Duo Processor and Intel
®
CoreTM Solo processor on 65nm process
AF = Dual-Core Intel
®
Xeon
®
processor LV
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and other Intel
products do not use this convention.
Errata (Sheet 1 of 3)
No. A0 Plans Description
D1 x No Fix Transaction is not retired after BINIT#
D2 x No Fix Invalid opcode 0FFFh requires a ModRM byte
D3 x No Fix Processor may hang due to speculative page walks to non-existent system memory
D4 x No Fix Memory type of the load lock different from its corresponding store unlock
D5 x No Fix Machine check architecture error reporting and recovery may not work as expected
D6 x No Fix Debug mechanisms may not function as expected
D7 x No Fix Cascading of performance counters does not work correctly when forced overflow is enabled
D8 x No Fix EMON event counting of x87 loads may not work as expected
D9 x No Fix
System bus interrupt messages without data and which receive a hard-failure response may hang the
processor
D10 x No Fix
The processor signals page fault exception (#PF) instead of alignment check exception (#AC) on an
unlocked CMPXCHG8B instruction
D11 x No Fix FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions
D12 x No Fix Processor issues inconsistent transaction size attributes for locked operation
D13 x No Fix When the processor is in the system management mode (SMM), debug registers may be fully writeable
D14 x No Fix
Shutdown and IERR# may result due to a machine check exception on a Hyper-Threading Technology
enabled processor
D15 x No Fix Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle
D16 x No Fix
System may hang if a fatal cache error causes bus write line (BWL) transaction to occur to the same
cache line address as an outstanding bus read line (BRL) or bus read-invalidate line (BRIL)
D17 x No Fix A write to APIC task priority register (TPR) that lowers priority may seem to have not occurred
D18 x No Fix Parity error in the L1 cache may cause the processor to hang
D19 x No Fix Locks and SMC detection may cause the processor to temporarily hang
D20 x No Fix Incorrect debug exception (#DB) may occur when a data breakpoint is set on an FP instruction
D21 x No Fix xAPIC may not report some illegal vector error
D22 x No Fix
Incorrect duty cycle is chosen when on-demand clock modulation is enabled in a processor supporting
Hyper-Threading Technology