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E7505 Chipset MCH Datasheet

3.5.18 DRA—DRAM Row Attribute Register (D0:F0)

Address Offset: 70–73h

Default Value: 00h

Attribute: RO, R/W

Size: 8 bits x 4 registers

The DRAM Row Attribute register defines the page sizes to be used for each row of memory. Each

nibble of information in the DRA registers describes the page size of a row. For this register, a row

is defined by the chip select used by the DIMM; thus, a double-sided DIMM has both an even and

an odd entry. For single-sided DIMMs, only the even side is used.

DRA Bits Row DRB

70h

3:0 Row0 DRB0

7:4 Row1 DRB1

71h

3:0 Row2 DRB2

7:4 Row3 DRB3

72h

3:0 Row4 DRB4

7:4 Row5 DRB5

73h

3:0 Row6 DRB6

7:4 Row7 DRB7

Bits

Default,

Access

Description

R/W

ODD Device Width. This bit defines the width of the DDR-SDRAM devices populated in

this row. This bit is used in the mapping of DQS signals to DQ signals, in the DDR-

SDRAM receive path.

0 = x8 or x16 DIMMs

1 = x4 DIMMs.

6:4

000b

R/W

ODD Row Attribute for Odd-numbered Row. This 3-bit field defines the page size of

the corresponding row.

000 = Reserved

001 = 4 KB

010 = 8 KB

011 = 16 KB

100 = 32 KB

101 = 64 KB

11x = Reserved

R/W

Even Device Width. This bit defines the width of the DDR-SDRAM devices populated in

this. This bit field is used in the mapping of DQS signals to DQ signals in the DDR-