Hub Datasheet

Signal Description
22 Intel
®
E7505 Chipset MCH Datasheet
Figure 2-1. MCH Interface Signals
CB_A[7:0]
DQ_A[63:0]
DQS_A[17:0]
CMDCLK_A[7:0], CMDCLK_A[7:0]#
MA_A[13:0]
BA_A[1:0]
RAS_A#
CAS_A#
WE_A#
CS_A[5:0]#
CKE_A[3:0]
RCVENOUT_A#
DRCOMP_H
DRCOMPVREF_H
DVREF_A
ODTCOMP
Hub
Interface
A
HI_A[11:0]
PSTRBF_0
PSTRBS_0
PRCOMP_A
PSWNG_A
PREF_A
Processor
System
Bus
Interface
HA[35:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
BREQ0#
DINV[3:0]#
HADSTB[1:0]#
HDSTBP[3:0]#/HDSTBN[3:0]#
AP[1:0]#
XERR#
BINIT#
DEP[3:0]#
RSP#
HDVREF[3:0]
HAVREF[1:0]
CCVREF
HXSWNG, HYSWNG
HXRCOMP, HYRCOMP
DDR
Channel
A
HCLKINP, HLCKINN
GCLKIN
PWRGD
RSTIN#
XORMODE#
TESTIN#
TESTSIG1
TESTSIG2
DDR_STRAP
VCCAGP
VCCAHI
VTT
VCCAFSB
VCCDDR
VCC
VSS
Clocks,
Reset,
and
Misc.
DDR
Channel
B
Hub
Interface
B
HI_B[21:20]
HI_B[18:0]
PSTRBF_B
PSTRBS_B
PUSTRBF_B
PUSTRBS_B
PRCOMP_B
PSWNG_B
PREF_B
AGP
Interface
SBA[7:0]
PIPE#
ST[2:0]
RBF#
WBF#
AD_STB[1:0], AD_STB[1:0]#
SB_STB, SB_STB#
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#
GAD[31:0]
GC/BE[3:0]#
GPAR
SERR#
—
PRCOMP_AGP0
PRCOMP_AGP1
PREF_AGP[1:0]
PSWNG_AGP[1:0]
CB_B[7:0]
DQ_B[63:0]
DQS_B[17:0]
CMDCLK_B[7:0], CMDCLK_B[7:0]#
MA_B[13:0]
BA_B[1:0]
RAS_B#
CAS_B#
WE_B#
CS_B[5:0]#
CKE_B[3:0]
RCVENOUT_B#
DRCOMP_V
DRCOMPVREF_V
DVREF_B
AGP 3.0
AGP 2.0
SBA[7:0]#
DBI_HI
ST[2:0]
RBF
WBF
AD_STBF[1:0], AD_STBS[1:0]
SB_STBF, SB_STBS
GFRAME
GIRDY
GTRDY
GSTOP
GDEVSEL
GREQ
GGNT
GAD[31:0]
GC#/BE[3:0]
GPAR
SERR
DBI_LO (3.0 only)
PRCOMP_AGP0
PRCOMP_AGP1
PREF_AGP[1:0]
PSWNG_AGP[1:0]