Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 157
Functional Description
The MCH supports re-directing lowest priority delivery mode interrupts to the processor which is
executing the lowest priority task thread. The MCH re-directs interrupts based on the task priority
status of each processor thread. The task priority of each processor thread is periodically
downloaded to the MCH via the xTPR (Task Priority Register) special transaction. The MCH re-
directs hub interface and PCI originated interrupts as well as IPIs.
The MCH also broadcasts EOI cycles generated by a processor downstream to the hub interface.
5.2 Hub Interface_A (HI_A)
The MCH’s 8-bit HI_A is used to connect to the ICH4. HI_A supports parallel termination. The
MCH uses Hub Interface 1.5 electricals on HI_A. HI_A also supports 64 bit upstream addressing
via the hub interface extended address mechanism.
5.3 Hub Interface_B (HI_B)
HI_B supports Hub Interface 2.0 only. The following assumptions apply to the HI_B:
• Supports HI 2.0 devices only
• Does not support 8-bit devices
• Does not operate in 1x mode
• Supports Hub Interface 2.0 Enhanced Parity (ECC) only
• Parallel termination only
• Does not support upstream writes or special cycles that require completion. The only upstream
cycle that can require a completion is a read.
• HI_B is designed to connect to the P64H2 component.