Hub Datasheet

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Intel

E7505 Chipset MCH Datasheet 15

Introduction

Introduction 1

The Intel

E7505 chipset is a high-performance chipset designed as the next generation

workstation. The main components of the chipset are the Memory Controller Hub (MCH) host

bridge and the Intel

82801BA I/O Controller Hub 4 (ICH4) for the I/O subsystem. A supporting

component for the platform is the Intel

82870P2 PCI-64 Hub 2 (P64H2) for I/O expansion.

The MCH is supports the Intel

Xeon™ processor with 512-KB L2 cache and the Intel

Xeon™

processor with 533 MHz system bus in dual-processor mode. Four-way processor mode is not

supported by the MCH. The MCH supports up to 16 GB of Double Data Rate (DDR) SDRAM

system memory and provides the next generation AGP 8x graphics port.

This document describes the E7505 chipset MCH. The MCH signals, registers, DC electrical

characteristics, ballout, package dimensions, and component testability are covered. The major

functional blocks of the MCH are described. For detailed descriptions of other chipset components,

refer to the respective component’s datasheet.

1.1 Terminology

Term Description

MCH

The Memory Controller Hub component contains the processor interface and system

memory interface. The MCH communicates with the I/O Controller Hub 4 (ICH4) and

other controller hubs over a proprietary interconnect called the Hub Interface.

The Hub Interface interconnects the MCH to the hub components (ICH4 or P64H2).

In this document HI cycles originating from or destined for the primary PCI interface

on the ICH4 are generally referred to as HI/PCI_A or simply HI_A cycles. Cycles

originating from or destined for any target on the second HI interface is described as

HI_B cycles.

NOTE: There are two versions of HI used on the MCH. An 8-bit HI1.5 protocol is

implemented on HI_A and a 16-bit HI2.0 protocol is implemented for the

HI_B.

Host This term is used synonymously with processor.

Inbound, refers to traffic moving from PCI or other I/O toward DRAM or the system

bus.

Intel

ICH4

The I/O Controller Hub 4 component contains the primary PCI interface, LPC

interface, USB 2.0, ATA-100 and other legacy functions. The ICH4 communicates

with the MCH over a proprietary interconnect called the Hub Interface, (HI1.5).

Intel

Xeon

Processor with 512-KB

L2 Cache

The MCH supports dual processors on a single 400 MHz system bus.

Intel

Xeon

Processor with

533 MHz System Bus

The MCH supports dual processors on a single 533 MHz system bus.

OB Outbound, refers to traffic moving from the system bus to PCI or other I/O.