Hub Datasheet

122 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.8 Hub Interface_B PCI-to-PCI Bridge Registers
(Device 2, Function 0)
The Hub Interface_B (HI_B) registers are in Device 2 (D2), Function 0 (F0). Table 3-6 provides
the register address map for this device, function.
Warning: Address locations that are not listed the table are considered reserved register locations. Writes to
“Reserved” registers may cause system failure. Reads to “Reserved” registers may return a non-
zero value.
Table 3-6. Hub Interface_B PCI-to-PCI Register Map (D2:F0)
Address
Offset
Mnemonic Register Name
Default
Value
Access
00–01h VID2 Vendor Identification 8086h RO
02–03h DID2 Device Identification 2553h RO
04–05h PCICMD2 PCI Command 0000h RO, RW
06–07h PCIST2 PCI Status 00A0h R/WC, RO
08h RID2 Revision Identification
See register
description
RO
0Ah SUBC2 Sub Class Code 04h RO
0Bh BCC2 Base Class Code 06h RO
0Dh MLT2 Master Latency Timer (scratch pad) 00h RO,RW
0Eh HDR2 Header Type 01h or 81h RO
18h PBUSN2 Primary Bus Number 00h RO
19h SBUSN2 Secondary Bus Number 00h RW
1Ah SUBUSN2 Subordinate Bus Number 00h RW
1Ch IOBASE2 I/O Base Address 00h RO
1Dh IOLIMIT2 I/O Limit Address F0h RO,RW
1E–1Fh SEC_STS2 Secondary Status 00h RW
20–21h MBASE2 Memory Base Address 02A0h RO,R/WC
22–23h MLIMIT2 Memory Limit Address FFF0h RO, RW
24–25h PMBASE2 Prefetchable Memory Base Address 0000h RO, RW
26–27h PMLIMIT2 Prefetchable Memory Limit Address FFF0h RO, RW
3Eh BCTRL2 Bridge Control 0000h RO, RW