Hub Datasheet

118 Intel

E7505 Chipset MCH Datasheet

R/W

Fast Write Enable (FWEN).

0 = Disable. When this bit it is 0 or when the data rate bits are set to 1x mode, the

Memory Write transactions from the MCH to the AGP master use standard PCI

protocol.

1 = Enable. MCH uses the Fast Write protocol for memory write transactions from the

MCH to the AGP master. Fast Writes occur at the data transfer rate selected by the

data rate bits (2:0) in this register.

NOTE: In 8x mode this bit is ignored since AGP 8x requires fast writes be supported.

This bit is functional in all modes except 1x mode.

3 Reserved

2:0

000b

R/W

Data Rate Enable (DRATE). The setting of these bits determines the AGP data transfer

rate. One (and only one) bit in this field must be set to indicate the desired data transfer

rate. The same bit must be set on both master and target. The encoding is determined

by the AGP 3.0 signaling mode bit in the AGPSTAT register.

Bits

Default,

Access

Description

Encoding AGP 2.0 Signaling AGP 3.0 Signaling

000 1x Transfer mode 4x Transfer mode

010 2x Transfer mode 8x Transfer mode

100 4x Transfer mode reserved