Hub Datasheet

102 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.5 RID1—Revision Identification Register (D1:F0)
Address Offset: 08h
Default Value: see table below
Attribute: RO
Size: 8 bits
This register contains the revision number of the MCH device 1. These bits are read only and
writes to this register have no effect.
3.7.6 SUBC1—Sub-Class Code Register (D1:F0)
Address Offset: 0Ah
Default Value: 04h
Attribute: RO
Size: 8 bits
This register contains the Sub-Class Code for the MCH device 1.
3.7.7 BCC1—Base Class Code Register (D1:F0)
Address Offset: 0Bh
Default Value: 06h
Attribute: RO
Size: 8 bits
This register contains the Base Class Code of the MCH device 1.
Bits
Default,
Access
Description
7:0
00h
RO
Revision Identification Number (RID). This is an 8-bit value that indicates the
revision identification number for the MCH device 1. It is always the same as the value
in RID.
03h = B-0 Stepping
Bits
Default,
Access
Description
7:0
04h
RO
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge
into which the device 1 of the MCH falls.
04h = PCI to PCI bridge.
Bits
Default,
Access
Description
7:0
06h
RO
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code
for the MCH device 1.
06h = Bridge device