Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
220 Datasheet
8.7 CL1—Cache Line Size
B/D/F/Type: 0/6/0/PCI
Address Offset: Ch
Default Value: 00h
Access: RW
Size: 8 bits
8.8 HDR1—Header Type
B/D/F/Type: 0/6/0/PCI
Address Offset: Eh
Default Value: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
8.9 PBUSN1—Primary Bus Number
B/D/F/Type: 0/6/0/PCI
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
Bit Access
Default
Value
Description
7:0 RW 00h
Cache Line Size (Scratch pad): Implemented by PCI Express devices as a
read-write field for legacy compatibility purposes but has no impact on any PCI
Express device functionality.
Bit Access
Default
Value
Description
7:0 RO 01h
Header Type Register (HDR): Returns 01h to indicate that this is a single
function device with bridge header layout.
Bit Access
Default
Value
Description
7:0 RO 00h
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device
#6 is an internal device and its primary bus is always 0, these bits are read only
and are hardwired to 0.