Datasheet

Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet 43
Pin Listing
DBI1# AD22 Source Sync Input/Output
DBI2# AE12 Source Sync Input/Output
DBI3# AB9 Source Sync Input/Output
DBSY# F18 Common Clk Input/Output
DEFER# C23 Common Clk Input
Don’t Care A2
Don’t Care A26
Don’t Care A28
Don’t Care A30
Don’t Care A31
Don’t Care B4
Don’t Care B26
Don’t Care B29
Don’t Care B30
Don’t Care B31
Don’t Care C2
Don’t Care C28
Don’t Care C31
Don’t Care D1
Don’t Care D25
Don’t Care D27
Don’t Care D29
Don’t Care E2
Don’t Care H1
Don’t Care H3
Don’t Care H5
Don’t Care H7
Don’t Care H9
Don’t Care K1
Don’t Care K3
Don’t Care K5
Don’t Care K7
Don’t Care K9
Don’t Care M1
Don’t Care M3
Don’t Care M5
Don’t Care M7
Don’t Care M9
Table 4-1. Pin Listing by Pin Name (Cont’d)
Pin Name Pin No.
Signal
Buffer Type
Direction
Don’t Care N1
Don’t Care N3
Don’t Care N5
Don’t Care N7
Don’t Care N9
Don’t Care R1
Don’t Care R3
Don’t Care R5
Don’t Care R7
Don’t Care R9
Don’t Care U1
Don’t Care U3
Don’t Care U5
Don’t Care U7
Don’t Care U9
Don’t Care AA4
Don’t Care AC4
Don’t Care AC30
Don’t Care AD6
Don’t Care AD30
Don’t Care AD31
Don’t Care AE2
Don’t Care AE3
Don’t Care AE8
Don’t Care AE15
Don’t Care AE16
DP0# AC18 Common Clk Input/Output
DP1# AE19 Common Clk Input/Output
DP2# AC15 Common Clk Input/Output
DP3# AE17 Common Clk Input/Output
DRDY# E18 Common Clk Input/Output
DSTBN0# Y21 Source Sync Input/Output
DSTBN1# Y18 Source Sync Input/Output
DSTBN2# Y15 Source Sync Input/Output
DSTBN3# Y12 Source Sync Input/Output
DSTBP0# Y20 Source Sync Input/Output
DSTBP1# Y17 Source Sync Input/Output
DSTBP2# Y14 Source Sync Input/Output
Table 4-1. Pin Listing by Pin Name (Cont’d)
Pin Name Pin No.
Signal
Buffer Type
Direction