User Manual

RoHS-compliant, lead-free technology
•ComplieswiththeEuropeanRoHSIIperDirective2011/65/EUoftheEuropeanParliament
Time Sync (IEEE 1588*, 802.1as)
(Normal Mode only)
•EnablesnetworkedEthernetequipmenttosynchronizeinternalclocksaccordingtoanetworkmas-
terclock;endpointcanthenacquireanaccurateestimateofthemastertimebycompensatingforlink
latency
SCSI Boot (Normal Mode only)
•EnablessystembootupviaiSCSI
•Providesadditionalnetworkmanagementcapability
I/O FEATURES FOR MULTI-CORE PROCESSOR SERVERS
(
SUPPORTED IN NORMAL MODE
)
Intel® Data Direct I/O (Intel® DDIO)
•ReducesmemoryaccessesfromI/Oonlocalsocket
•SpeedsupCPUdatatransfer
•Acceleratesinbound&outbounddataows
Intel® Ethernet Flow Director
•IntelEthernetFlowDirectorandATRcansignicantlylowerlatencyandimproveCPUutilizationby
preservingtheafnitybetweentheowandthecorewheretheapplicationresides
RSS—Receive Side Scaling
•Usesmultiplequeuesforreceivetrafc
Intel® Direct Cache Access (DCA)
•Enablestheadaptertopre-fetchthedatafrommemory,avoidingcachemissesandimprovingapplica-
tionresponsetime
MSI-X support
•Minimizestheoverheadofinterrupts
•Load-balancingofinterrupthandlingbetweenmultiplecores/CPUs
Low Latency Interrupts (LLI)
•Basedonthesensitivityoftheincomingdata,theadaptercanbypasstheautomaticmoderationof
timeintervalsbetweentheinterrupts
Multiple Queues: 128 Tx & Rx queues per port
•Networkpackethandlingwithoutwaitingorbufferoverowprovidingefcientpacketprioritization
Tx/Rx IP, SCTP, TCP, & UDP checksum
off-loading (IPv4, IPv6) capabilities
•Lowerprocessorusage
•Checksumandsegmentationcapabilityextendedtonewstandardpackettype
TxTCP segmentation off-load (IPv4, IPv6)
•Increasedthroughputandlowerprocessorusage
Interrupt Throttle Rate
(
ITR
)
•ITRparametercontrolshowmanyinterruptseachinterruptvectorcangeneratepersecond.
Jumbo frames
•Supportsjumboframeslargerthandefault1500
Large Receive Off-load (LRO)
•CombinesmultipleEthernetframesintoasinglereceiveinthestack,therebypotentiallydecreasing
CPUutilizationforreceives
MAC and VLAN anti-spoong
•Ifamaliciousdriverattemptstosendaspoofedpacket,itisdroppedbythehardwareandnottransmit-
ted.AninterruptissenttothePFdrivernotifyingitofthespoofattempt.
Flow Control
•EthernetFlowControl(IEEE802.3x)supportforcapablelinkpartner
HW based receive side coalescing (RSC)
•MergesmultipleframesfromthesameIPv4TCP/IPflowintoasinglestructurethatcanspanoneor
moredescriptors
VIRTUALIZATION FEATURES
(
SUPPORTED IN NORMAL MODE
)
PC-SIG SR-IOV Implementation (up to 64
virtual functions per port)
•ProvidesanimplementationofthePCI-SIGstandardforI/OVirtualization.Thephysicalconguration
ofeachportisdividedintomultiplevirtualports.Eachvirtualportisassignedtoanindividualvirtual
machinedirectlybybypassingthevirtualswitchintheHypervisor,resultinginnear-nativeperfor-
mance.
•IntegratedwithIntel®VTforDirectedI/O(Intel®VT-d)toprovidedataprotectionbetweenvirtual
machinesbyassigningseparatephysicaladdressesinthememorytoeachvirtualmachine.
Advanced Packet Filtering
•24exact-matchedpackets(unicastormulticast)
•4096-bithashlterforunicastandmulticastframes
•Lowerprocessorusage
•Promiscuous(unicastandmulticast)transfermodesupport
•Optionallteringofinvalidframes
VLAN support with VLAN tag insertion, stripping
and packet ltering for up to 4096 VLAN tags
•AbilitytocreatemultipleVLANsegments
GENERAL SPECIFICATIONS
Connectors
TwoLC10GBASE-SR(X520-SR2)(Opticsnotremovable)
TwoLC10GBASE-LR(X520-LR2)(Opticsnotremovable)
TwoRJ-45Copper(X540)
Data rates supported per port:
X520
X540

Optical:1GbE/10GbE
Copper:100Mbps/1GbE/10GbE
Bus type
PCIExpress2.0(5.0GT/s)(X520)
PCIExpress2.1(5.0GT/s)(X540)
Bus widths
8-lanePCIExpress(X520&X540)
3