Datasheet

Technical Reference

Table 3 lists the supported DIMM configurations.

Table 3. Supported Memory Configurations

DIMM

Capacity

Configuration

(Note 1)

SDRAM

Density

SDRAM Organization

Front-side/Back-side

Number of SDRAM

Devices

(Note 2)

1024 MB SS 1 Gb 128 M x 8/empty 8 [9]

2048 MB DS 1 Gb 128 M x 8/128 M x 8 16 [18]

Notes:

1. In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM)

and “SS” refers to single-sided memory modules (containing one row of SDRAM).

2. In the fifth column, the number in brackets specifies the number of SDRAM devices on an ECC DIMM.

1.5.1 Memory Configurations

The Intel

Xeon

W3500 series Processor supports the following types of memory

organization:

 Tri/Dual channel (Interleaved) mode. This mode offers the highest throughput

for “real world” applications. Interleaving reduces overall memory latency by

accessing the DIMM memory sequentially. Data is spread amongst the memory

modules in an alternating pattern.

 Three independent memory channels give two possible modes of interleaving:

 Tri-Channel Mode: Enabled when identical matched memory modules are

installed in each of the three memory channels (blue connectors).

 Dual-Channel Mode: Enabled when two of the blue memory connectors

are populated with matched DIMMs.

 Single-Channel (Asymmetric) Mode: Equivalent to single-channel bandwidth

operation for real world applications. This mode is used when only a single DIMM is

installed or the installed memory modules are not matched. Technology and device

width can vary from one channel to the other.

Figure 3 illustrates the memory channel and DIMM configuration.