Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Datasheet 57
Package Mechanical Specifications and Pin Information
§
THERMTRIP# Output
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
For termination requirements please contact your Intel
representative.
TMS Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
Please contact your Intel representative for termination
requirements and implementation details.
TRDY# Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
Please contact your Intel representative for termination
requirements and implementation details.
TRST# Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
Please contact your Intel representative for termination
requirements and implementation details.
V
CC
Input Processor core power supply.
V
CCA
Input
V
CCA
provides isolated power for the internal processor core PLL’s.
Please contact your Intel representative for complete
implementation details.
V
CCP
Input Processor I/O Power Supply.
V
CCSENSE
Output
V
CCSENSE
together with V
SSSENSE
are voltage feedback signals to
IMVP6 that control the 2.1-mΩ loadline at the processor die. It
should be used to sense voltage near the silicon with little noise.
Please contact your Intel Representative for more information
regarding termination and routing recommendations.
VID[6:0] Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (V
CC
). Unlike some previous generations
of processors, these are CMOS signals that are driven by the Intel
Core Duo processor and Intel Core Solo processor. The voltage
supply for these pins must be valid before the VR can supply V
CC
to
the processor. Conversely, the VR output must be disabled until the
voltage supply for the VID pins becomes valid. The VID pins are
needed to support the processor voltage specification variations.
See Table 2 for definitions of these pins. The VR must supply the
voltage that is requested by the pins, or disable itself.
V
SSSENSE
Output
V
SSSENSE
together with V
CCSENSE
are voltage feedback signals to
Intel® MVP6 that control the 2.1-mΩ loadline at the processor die.
It should be used to sense ground near the silicon with little noise.
Please contact your Intel Representative for more information
regarding termination and routing recommendations.
Table 17. Signal Description (Sheet 9 of 9)
Name Type Description