Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.
Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Applications............................................................................................................... 9 1.1 Introduction and Terminology ............................................................................... 9 2 Output Voltage Requirements.................................................................................. 11 2.1 Voltage and Current - REQUIRED......................................................................... 11 2.
8.10 Safety - PROPOSED ...........................................................................................46 9 Manufacturing Considerations..................................................................................47 9.1 Lead Free (Pb Free) ...........................................................................................47 A Z(f) Constant Output Impedance Design ..................................................................49 A.1 Introduction - PROPOSED ....................
2-6 Recommended Decoupling and Other Specifications for Supported (Highest SKU) Processors - Summary .................................................................. 22 2-7 Dual-Core Intel Xeon Processor-Based Server/Dual-Core Intel Xeon Processor-Based Server-VS/Dual-Core Intel Xeon Processor-Based Workstation Platform Processor Decoupling Capacitor Recommendations .................. 24 2-8 ..................................................................................................................
Revision History Rev # 6 Description Rev.
The following table lists the revision schedule based on revision number and development stage of the product. Revision Project Document State Projects Covered 0.5 Preliminary Targets HW, SW 0.5 to 0.9 Updates to Most Recent Update or 0.5 HW, SW 1.0 Design Frozen HW, SW 1.0 to 1.5 Updates to Most Recent Update or 1.0 HW, SW 1.5 Preliminary Validation Data (Doc-Dependent) HW Only 1.6 to 1.75 Updates to Most Recent Update or 1.5 HW Only 1.
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Applications 1 Applications 1.1 Introduction and Terminology This document defines the DC-to-DC converters to meet the processor power requirements of the following platforms: Table 1-1. VRM/EVRD 11.
Applications • New power-on sequence • Extended VR 10.x VID table with a 7th bit for 6.25 mV resolution and 0.83125 V to 1.6 V range, only 12.5 mV resolution will be used in Dual-Core Intel Xeon Processor-Based Platform and Intel E8500 platforms. • Support for a separate additional VR 11.0 VID table with a 8-bit table and 6.25 mV resolution with a 31.25 mV to 1.6 V VID range, only 12.
Output Voltage Requirements 2 Output Voltage Requirements 2.1 Voltage and Current - REQUIRED There will be independent selectable voltage identification (VID) codes for the core voltage regulator. The VID code is provided by the processor to the VRM/EVRDs, which will determine a reference output voltage, as described in Section 3.2. As previously mentioned, the VR 11.0 controller will support two VID tables: 1. An extended 7-bit VR 10.x table, ranging from 0.83125 V to 1.6 V 2. An 8-bit VR11.
Output Voltage Requirements The continuous load current (ICCTDC) can also be referred to as the Thermal Design Current (TDC). It is the sustained DC equivalent current that the processor is capable of drawing indefinitely and defines the current that is used for the voltage regulator temperature assessment. At TDC, switching FETs may reach maximum allowed temperatures and may heat the baseboard layers and neighboring components.
Output Voltage Requirements Table 2-2.
Output Voltage Requirements The upper and lower load lines represent the allowable range of voltages that must be presented to the processor. The voltage must always stay within these boundaries for proper operation of the processor. Operating above the VCCMAX load line limit will result in higher processor operating temperature, which may result in damage or a reduced processor lifespan.
Output Voltage Requirements Table 2-3. VID_Select, LL1, LL0 Codes (Sheet 2 of 2) VR11.0 mode VR10.2 mode VID Table VID_ Select LL1 LL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Load Line / Processors VccMAX = VID (V) –1.25 mΩ • Icc (A) VccMIN = VID (V) –1.25 mΩ • Icc (A) –30 mV VccMAX = VID (V) –1.25 mΩ • Icc (A) VccMIN = VID (V) –1.25 mΩ • Icc (A) –30 mV VccMAX = VID (V) –1.25 mΩ • Icc (A) VccMIN = VID (V) –1.
Output Voltage Requirements 2.4 Processor VCC Overshoot - REQUIRED The VRM/EVRD 11.0 is permitted short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high-to-low current load condition (Figure 2-2). This overshoot cannot exceed VID + VOS_MAX. The overshoot duration, which is the time that the overshoot can remain above VID, cannot exceed TOS_MAX.
Output Voltage Requirements dependent upon the selection of the bulk capacitors, ceramic capacitors, power plane routing and the tuning of the PWM controller’s feedback network. This analysis can be done with LGA771-V2 VTT tool impedance testing or through power delivery simulation if the designer can extract the parasitic resistance and inductance of the power planes on the motherboard along with good models for the decoupling capacitors.
Output Voltage Requirements 3. Table 2-4. See Section 2.5 and Table 2-4, Impedance Measurement parameters and definitions Impedance ZLL Measurement Parameter Limits Processor ® Dual-Core Intel Xeon ® Processor 5000 Series Dual-Core Intel® Xeon® Processor 5000 Series MV Dual-Core Intel® Xeon® Processor X5100 Series -Perf. Dual-Core Intel® Xeon® Processor E5100 Series ® Dual-Core Intel ZLLMin 3 Fbreak 1.25 mΩ 1.45 mΩ 1.05 mΩ 2.0 MHz 1.25 mΩ 1.511 mΩ 0.989 mΩ 2.0 MHz 1.25 mΩ 1.
Output Voltage Requirements Figure 2-4. Power-On Sequence Timing Diagram BCLK [1:0] (for reference only) PWM Vcc (5V/12V) Tf Ta VTT VTT_PWRGD OUTEN VID_SELECT Tg (pulled up to VTT) Tc VBOOT=1.1V Vcc_CPU Te Td Tb VR_READY VID code read by PWM at the end of Tc VID bits VID valid / BSEL[2:0] CPU_PWGOOD (from platform, for reference only) RESET# (for reference only) VCCPLL (for reference only) Notes: 1. VTT_PWRGD can be designed to be driving directly the OUTEN input. 2.
Output Voltage Requirements Table 2-5. Startup Sequence Timing Parameters (Sheet 2 of 2) Timing Td = VccCPU rise time to final VID Min Default Max 0 0.25 ms 2.5 ms Te = VccCPU to VR_READY assertion time 0.05 ms 3.0 ms Tf = Vtt rise time 0.05 ms 10.0 ms 0 5.0 ms Tg = OUTEN to Vcc_CPU rising delay time Remarks Programmable soft start ramp; Measured from 10-90% of slope Measured from 10-90% of slope Note: 1.
Output Voltage Requirements Figure 2-5. Processor Transition States VID High Load Line 2 A 3 Icc-max 5 VID Low Load Line 1 B 4 Figure 2-6 is an example of dynamic VID. The diagram assumes steady state, constant current during the dynamic VID transition for ease of illustration; actual processor behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that time.
Output Voltage Requirements 2.9 Overshoot at Turn-On or Turn-Off - REQUIRED The core VRM/EVRD output voltage should remain within the load-line regulation band for the VID setting, while the VRM/EVRD is turning on or turning off, with no over or undershoot out of regulation. No negative voltage below –100 mV may be present at the VRM/EVRD output during turn-on or turn-off. 2.10 Output Filter Capacitance - REQUIRED The output filter capacitance for the VRM/EVRD11.
Output Voltage Requirements Figure 2-7. Six-layer Dual-Core Intel Xeon Processor-Based Server Platform VccP Power Delivery Impedance Model Path with 1206 Size Caps VR Motherboard 15 X 560 uF Aluminum-Polymer 8400 uF 350 uF 0.40m 0.09m 267 pH Figure 2-8. 58 pH 9 X 10 uF MLCC 1206 0.51m 20 pH 0.33m 90 uF VR Sense Point 0.
Output Voltage Requirements Note: The amount of bulk decoupling needed is dependent on the voltage regulator design. Some multiphase buck regulators may have a higher switching frequency that would require a different output decoupling solution to meet the processor load line requirements than described in this document. Table 2-7.
Output Voltage Requirements Figure 2-10. Dual-Core Intel Xeon 5000 Series with Intel 5400 Chipsets Platform VccP Power Delivery Impedance Model Path - Example Motherboard VR Low Fr Caps 12x 560µF Oscon Socket & Package HF Caps 49x 10µF 0.51 mO MLCC 1206 Mid Fr Caps 10x 100µF MLCC 1210 20 pH 54 pH 6.72mF 0.33 mO 490µF 1mF 0.58 mO 0.4 mO 0.33 nH 52 pH HF Caps in socket cavity 9x 10µF MLCC 1206 90µF Sense Point 30A to 130A 1000A/us 0.56 mO 0.08 mO 20 pH 0.11 nH Table 2-10.
Output Voltage Requirements 2.11 Shut-Down Response - REQUIRED Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. If the extended VR 10 VID table is selected, the VRM/EVRD should turn off its output if VID [6:0] = XX11111. If the VR 11.
Control Signals 3 Control Signals 3.1 Output Enable (OUTEN) - REQUIRED The VRM/EVRD must accept an input signal to enable its output voltage. When disabled, the regulator’s output should go to a high impedance state and should not sink or source current. When OUTEN is pulled low during the shutdown process, the VRM/EVRD must not exceed the previous voltage level regardless of the VID setting during the shutdown process. Once operating after power-up, it must respond to a deasserted OUTEN within 500 ms.
Control Signals Table 3-3.
Control Signals Table 3-4. VR 11.0 Voltage Identification (VID) Table Note: 3.3 Only VID [6.0] are used for VRM/EVRD 11.0 platforms. The eighth VID bit is provisional for future Itanium-based platforms. Differential Remote Sense (VO_SEN+/-) REQUIRED The PWM controller shall include differential sense inputs to compensate for an output voltage offset of less than 300 mV in the power distribution path.
Control Signals Figure 3-1. Remote Sense Routing example. High Impedance Path 1k LGA 771 Socket Pin AL8 Pin AL7 1 of 9 10µF In µP Cavity Pin AN3 Pin AN4 1% VCC_ DIE_ SENSE2 10 1% 10 1% 10 1% 10 1% VSS_ DIE_ SENSE2 VCC_ DIE_ SENSE VSS_ DIE_ SENSE VCC/ VSS Feedback Inputs EVRD11.0 Controller or VRM 11.0 Connector High Impedance Path 1k 1% Notes: For each processor, refer to the appropriate platform design guide (PDG) for the recommended VR’s remote sense routing.
Control Signals 3.4 Load Line Select (LL0, LL1, VID_Select) REQUIRED The VID_Select, LL1 and LL0 control signal form a 3-bit load line selection and will used to configure the VRM/EVRD to supply the proper load line for the processors. These signals are programmed by the CPU package pin bonding. The VID_Select control signal will select the appropriate VR10 or VR11 VID table and remap the VID [6:0] pins to the appropriate DAC input. The signals are open-collector/drain or equivalent signals.
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Input Voltage and Current 4 Input Voltage and Current 4.1 Input Voltages - EXPECTED The power source for the VRM/EVRD is 12 V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down. 4.2 Load Transient Effects on Input Current EXPECTED The design of the VRM/EVRD, including the input power delivery filter, must ensure that the maximum slew rate of the input current does not exceed 0.
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Processor Voltage Output Protection 5 Processor Voltage Output Protection These are features built into the VRM/EVRD to prevent fire, smoke or damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) - EXPECTED The OVP circuit monitors the processor core voltage (Vcc) for an over-voltage condition. If the output is more than 200 mV above the VID level, the VRM/EVRD shuts off the output. 5.
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Output Indicators 6 Output Indicators 6.1 Voltage Regulator Ready (VR_Ready) - REQUIRED The VRM/EVRD VR_Ready signal is an output signal that indicates the start-up sequence is complete and the output voltage has moved to the programmed VID value. This signal will be used for start-up sequencing for other voltage regulators, clocks, and microprocessor reset. This signal is not a representation of the accuracy of the DC output to its VID value.
Output Indicators to the FORCEPR# pin or through system management logic. Assertion of this signal will lower processor power consumption and reduce current draw through the voltage regulator, resulting in lower component temperatures. Sustained assertion of the FORCEPR# pin will cause noticeable platform performance degradation and should not occur when drawing less than the specified thermal design current for a properly designed system.
Output Indicators non-valid code VR 11.0 mode VR 10.2 mode Figure 6-1. VRM 11.0 and Platform Present Detection VRID# VRM_Pres# VID_SELECT LL1 (MB LL0 (MB (MB Pull UP, (MB Pull-up, (VRM Pulldwn, PullUP, PullUP, CPU Pull CPU Pull VRM PullPlatform VRM Pull DWN) DWN) DWN) pullup) DWN) 0 0 0 0 0 0 0 0 0 1 Outcome VRD11.0 Module (130Atdc, 150Apk, VID11.0 and VID10.2 compat, 30mV tol) Outcome in VRM11.
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VRM – Mechanical Guidelines 7 VRM – Mechanical Guidelines 7.1 VRM Connector - EXPECTED The part number and vendor name for VRM 11.0 connectors that can be found in Table 7-1. The VRM reference in Section 7.2, Section 7.3 and Section 7.4, is based on the Tyco*/Elcon* interface with the system board is a 27-pin pair edge connector. The connector uses latches to hold the VRM in place. The connector will be rated to handle a continuous load current of 130 A. Table 7-1. VRM 11.
VRM – Mechanical Guidelines Table 7-2. VRM 11.0 Connector Pin Descriptions Name Description Load_Current Output Analog signal representing the output load current OUTEN Input Output enable VR_Ready Output Output signal indicating that the start-up sequence is complete and the output voltage has moved to the programmed VID value.
VRM – Mechanical Guidelines Figure 7-1. VRM 11.0 Pin Assignments KEY KEY KEY 7.
VRM – Mechanical Guidelines Figure 7-1. VRM 11.0 Module and Connector 96.52mm (3.80") MAX 51.84mm (2.04”) 2X R2.00mm (R0.08") Component Keepout 1.70mm (0.067") 22.97mm (0.904") 28.9mm (1.138") 22.88mm (0.901") 10.16mm (0.4") MAX 93.34mm (3.675") MAX View A 14.27mm (0.562") MAX FAR SIDE Components OPEN Latches 114.98mm (4.527") MAX CLOSED Latches 102.5mm (4.035") MAX Connector Length 97.54mm (3.840") MAX 66.77mm (2.629") 36.07mm (1.420") 9.70mm (0.382") 10.53mm(0.415") 6.00mm (0.236") 1.
Environmental Conditions 8 Environmental Conditions The VRM/EVRD design, including materials, should meet the environmental requirements specified below. 8.1 Operating Temperature - PROPOSED The VRM/EVRD shall meet all electrical requirements when operated at the Thermal Design Current (IccTDC) over an ambient temperature range of 0ºC to +45ºC with a minimum airflow of 400 LFM (2 m/s). The volumetric airflow (Q) can be measured through a wind tunnel.
Environmental Conditions 8.5 Altitude - PROPOSED 3.05 km [10 k feet] – operating 15.24 km [50 k feet] – non-operating 8.6 Electrostatic Discharge - PROPOSED Testing shall be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level. The direct ESD event shall cause no out-ofregulation conditions – including overshoot, undershoot and nuisance trips of overvoltage protection, over-current protection or remote shutdown circuitry. Non-operating –25 kV initialization level.
Manufacturing Considerations 9 Manufacturing Considerations 9.1 Lead Free (Pb Free) The use of lead in electronic products is an increasingly visible environmental and political concern. The drivers for the reduction or elimination of lead in electronic products include: • Customer desire for environmentally friendly (‘green’) products. • Manufacturer desire to be environmentally friendly, and be perceived as such. • Government initiatives regarding recycling of electronic products.
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Z(f) Constant Output Impedance Design A Z(f) Constant Output Impedance Design A.1 Introduction - PROPOSED The VRM/EVRD performance specification is based on the concept of output impedance, commonly known as the load line. The impedance is determined by the Pulse Width Modulator (PWM) controller’s Adaptive Voltage Positioning (AVP), up to the loop bandwidth of the regulator and the impedance of the output filter and socket beyond the loop bandwidth. Figure A-1.
Z(f) Constant Output Impedance Design Figure A-2. Z(f) Network Plot with 1.25 mΩ Load Line The impedance plot Z(f) shown in Figure A-2 can be divided up into three major areas of interest. • Low frequency, Zero Hz (DC) to the VR loop bandwidth. This is set by AVP and loop compensation of the VR controller or PWM control IC. • Middle frequency, VR loop bandwidth to socket inductance rise - This is set by the bulk capacitors, MLCC capacitors and PCB layout parasitic elements.
Z(f) Constant Output Impedance Design capacitors in parallel. The effect of the mid frequency resonant point must be investigated and validated with Vdroop testing to ensure any current load transient pattern, does not violate the Vmin load line. By defining the output impedance load line over a frequency range, the voltage regulation or voltage droop is defined at any current level as the output current multiplied by the impedance value.
Z(f) Constant Output Impedance Design frequency applied by the application. Hence a better method is needed to extract the impedance profile with the VR operating. The following sections introduce the theory behind using a VTT tool to create an impedance profile for the VR system. A.2 Voltage Transient Tool (VTT) Z(f) Theory The following expression is the definition of impedance as a function of frequency looking back from the VTT tool into the filter network and VRM.
Z(f) Constant Output Impedance Design Figure A-4. Time Domain Responses and Corresponding Fourier Spectra of Voltage, Current and Impedance A.3 VTT Z(f) Measurement Method An electronic load that has the capability to change the repetition rate up to 3 MHz of the load step is needed. The Intel LGA771/775V2 VTT by Cascade Systems Design, will meet this requirement.
Z(f) Constant Output Impedance Design current was 40 A. The waveforms show the effect of capacitor depopulation on the impedance profile above 1 MHz as pairs of high frequency MLCC capacitors are removed (banks 1-9) per the bank designations depicted in Figure A-7. Simulation comparisons are made in Figure A-8 for the two extreme cases of the decoupling conditions of Figure A-7, with all MLCC plus two Al-Poly bulk capacitors in place and all cavity MLCCs plus two Al-Poly bulk capacitors removed.
Z(f) Constant Output Impedance Design Figure A-6. Measured Platform Impedance Profile Showing Change in Impedance as Capacitors Are Removed Magnitude of impedance profile 10 9 8 magnitude (mohms) 7 6 5 4 all caps installed 1. 2x 10uF removed 2. 2x 10uF removed 3. 2x 10uF removed 4. 2x 22uF removed 5. 10, 22 uF removed 6. 2x 22uF removed 7. 10, 22uF removed 8. 2x 10uF removed 9. 2x 22uF removed MLCC + 1 Bulk removed MLCC +2 Bulk removed 3 2 1 0 0.001 0.01 0.
Z(f) Constant Output Impedance Design Figure A-8. Simulated and Measured Waveforms of Platform Impedance Profile measured vs simulated results 10 9 8 impedance (mohms) 7 meas:allcaps meas:bank1-9+2oscons sim:swvr-allcaps sim:avgvr-allcaps sim:swvr-bank1-9+2osc sim:avgvr-bank1-9+2osc 6 5 4 3 2 1 0 -3 10 A.5 -2 10 -1 0 10 10 frequency(MHz) 1 10 Output Decoupling Design Procedure 1. Select type and number of bulk capacitors.
