Intel Core2 Duo Processor E8000 and E7000 Series Specification Update

Summary Tables of Changes
12 Intel
®
Core
™
2 Duo Processor
Specification Update – December 2010
NO
C0 M0 E0 R0 Plan
ERRATA
AW61 X X No Fix
Processor May Hold-off / Delay a PECI Transaction Longer
than Specified by the PECI Protocol
AW62 X No Fix
VM Entry May Use Wrong Address to Access Virtual-APIC
Page
AW63 X X No Fix XRSTOR Instruction May Cause Extra Memory Reads
AW64 X X Plan Fix CPUID Instruction May Return Incorrect Brand String
AW65 X No Fix
Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
AW66 X X No Fix
When Intel
®
Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AW67 X X No Fix
Enabling PECI via the PECI_CTL MSR incorrectly
writes CPUID_FEATURE_MASK1 MSR
AW68 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AW69 X X X X No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
AW70 X X X X No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AW71 X X No Fix
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
AW72 X X No Fix
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
AW73 X X No Fix Store Ordering Violation When Using XSAVE
AW74 X X X X No Fix
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
AW75 X X Plan Fix
Unsynchronized Cross-Modifying Code Operations Can
Cause Unexpected Instruction Execution Results
AW76 X X X X No Fix
A Page Fault May Not be Generated When the PS bit is set
to “1” in a PML4E or PDPTE
AW77 X X X X No Fix
Not-Present Page Faults May Set the RSVD Flag in the Error
Code
AW78 X X X X No Fix
VM Exits Due to “NMI-Window Exiting” May Be Delayed by
One Instruction
AW79 X X X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated
After an FP Access Which Wraps a 4-Gbyte Boundary in
Code That Uses 32-Bit Address Size in 64-bit Mode
AW80 X X No Fix
VM Entry May Overwrite the Value for the IA32_DEBUGCTL
MSR Specified in the VM-Entry MSR-Load Area
AW81 X X X X No Fix
A 64-bit Register IP-relative Instruction May Return
Unexpected Results