Intel Core2 Duo Processor E8000 and E7000 Series Specification Update

Summary Tables of Changes
Intel
®
Core
™
2 Duo Processor
Specification Update – December 2010 9
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and
other Intel products do not use this convention.
NO
C0 M0 E0 R0 Plan
ERRATA
AW1 X X X X No Fix
EFLAGS Discrepancy on Page Faults after a Translation
Change
AW2 X X X X No Fix
INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
AW3 X X X X No Fix
Store to WT Memory Data May be Seen in Wrong Order by
Two Subsequent Loads
AW4 X X X X No Fix
Non-Temporal Data Store May be Observed in Wrong
Program Order
AW5 X X X X No Fix
Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
AW6 X X X X No Fix
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
AW7 X X X X No Fix
Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
AW8 X X X X No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
AW9 X X X X No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
AW10 X X X X No Fix
Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
AW11 X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AW12 X X X X No Fix
Code Segment limit violation may occur on 4 Gigabyte limit
check
AW13 X X X X No Fix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
AW14 X X X X No Fix
Last Branch Records (LBR) Updates May be Incorrect after a
Task Switch
AW15 X X X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-
Ordering Violations
AW16 X X X X No Fix
Upper 32 bits of ‘From’ Address Reported through BTMs or
BTSs May be Incorrect
AW17 X X X X No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
AW18 X X X X No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
AW19 X X X X No Fix
Store Ordering May be Incorrect between WC and WP
Memory Types