Intel Core2 Duo Processor E8000 and E7000 Series Specification Update

Errata
38 Intel
®
Core
™
2 Duo Processor
Specification Update – December 2010
AW54. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
Problem: IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to
indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at
the time of the last update to the IA32_MC1_STATUS MSR. Due to this
erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of
the IA32_MC1_CTL MSR enable bit.
Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the
enable bit in the IA32_MC1_CTL MSR at the time of the last update.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW55. A VM Exit Due to a Fault While Delivering a Software Interrupt May
Save Incorrect Data into the VMCS
Problem: If a fault occurs during delivery of a software interrupt (INTn) in virtual-8086
mode when virtual mode extensions are in effect and that fault causes a VM
exit, incorrect data may be saved into the VMCS. Specifically, information
about the software interrupt may not be reported in the IDT-vectoring
information field. In addition, the interruptibility-state field may indicate
blocking by STI or by MOV SS if such blocking were in effect before execution
of the INTn instruction or before execution of the VM-entry instruction that
injected the software interrupt.
Implication: In general, VMM software that follows the guidelines given in the section
“Handling VM Exits Due to Exceptions” of Intel
®
64 and IA-32 Architectures
Software Developer’s Manual Volume 3B: System Programming Guide should
not be affected. If the erratum improperly causes indication of blocking by
STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed
by one instruction.
Workaround: VMM software should follow the guidelines given in the section “Handling VM
Exits Due to Exceptions” of Intel
®
64 and IA-32 Architectures Software
Developer’s Manual Volume 3B: System Programming Guide.
Status: For the steppings affected, see the Summary Tables of Changes.
AW56. A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort
When Expected
Problem: If a VM exit occurs while the processor is in IA-32e mode and the “host
address-space size” VM-exit control is 0, a VMX abort should occur. Due to
this erratum, the expected VMX aborts may not occur and instead the VM Exit
will occur normally. The conditions required to observe this erratum are a VM
entry that returns from SMM with the “IA-32e guest” VM-entry control set to
1 in the SMM VMCS and the “host address-space size” VM-exit control cleared
to 0 in the executive VMCS.