Family paper

Appendix A: Architectural Overview
6 MB
Core
Caching agent
L3
P&T Controller
Configuration
QPI
6 MB
Core
Caching agent
L3
6 MB
Core
Caching agent
L3
6 MB
Core
Caching agent
L3
Home agent
Memory controller
Home agent
Memory controller
Router
1 MB Directory
Cache
1 MB Directory
Cache
Intel® Scalable Memory
Interconnect (Intel® SMI)
12
White Paper: The Intel® Itanium® Processor 9300 Series
Processing
Four cores per processor
Individual cores are very similar to the cores in the previous Intel® Itanium® processor 9000 series, but with signicant enhancements to
improve performance and virtualization
Dedicated cache per core
• L1: Instruction (16 KB), Data (16 KB)
• L2: Instruction (512 KB), Data (256 KB)
• L3: Cache (6 MB)
Similar to the Intel Itanium processor 9000 series. Maintains 128 byte L2 and L3 cache line size, so existing code remains optimized in
the new processor.
Dedicated Caching Agent per core
Interfaces the core with the Intel® QuickPath Interconnect technology router. Supports 64 concurrent transactions and converts 128-byte
cache lines to the 64-byte Intel QuickPath Interconnect technology protocol.
Conguration Agent
Manages conguration and interrupt requests and interfaces with side band external interfaces, such as SMBus and ash ROM.
Power & Thermal (P&T) Controller
Enables dynamic voltage and frequency control to optimize performance versus energy consumption as desired. Also interfaces with
thermal trip points and can trigger throttling to protect against over-heating and preserve data integrity.
Memory
Two Integrated Memory Controllers
Each memory controller can schedule memory commands at up to 4.8 GT/s and supports: DRAMs running at 800 MHz; up to 48 concurrent
DRAM commands; several policies for keeping DRAM pages closed following an access.
Dedicated Home Agent per Controller
Maintains cache coherency using true directory-based coherency (1 MB directory per controller), to improve scalability in large SMP
congurations. Tracks Exclusive, Shared, Coarse Shared or Invalid status, plus a coarse sharing vector, for each cache line. Supports up
to 32 pending transactions.
Memory Channel Links (PHY Layers)
Each link supports 4.8 GT/s transfer rates and lane and polarity reversal for exible board level routing.
Intel® Scalable Memory Interconnect
A high performance serial differential interface that can connect with a memory buffer to expand narrow CPU interfaces to wide
DDR3 interfaces.
System Interconnect
Intel® QuickPath Interconnect Technology
Router
12-port crossbar router with dedicated ports for each of the six Intel QuickPath Interconnect links, the two Home Agents and the four
Caching Agents. Can route packets from any port to any port. Supports high-speed, high-reliability point-to-point communications among
processor cores and between the cores and connected I/O devices.
Intel® QuickPath Interconnect Physical
Links (PHY Layers)
Each link supports 4.8 GT/s transfer rates and lane and polarity reversal for exible board level routing. Full width Intel QuickPath Interconnect
Technology links are 20 bits wide with differential signaling per direction.