Applications paper
Resteer—correcting the rare errors that cannot be fixed in
hardware
There is another class of soft errors that are not directly cor-
rectable in hardware, but are detected and can be corrected by
processor rmware. These errors are handled by a “resteer”
operation. During a resteer, the OS or application is interrupted
and processor rmware is executed to correct the error. The
rmware takes appropriate actions to remove the error from
hardware and then restarts the OS or application where it left
off.
Resteers are used to correct soft errors in translation lookaside
buffers (TLBs) and in general purpose and oating point register
les. However, these error scenarios are relatively rare. The vast
majority of soft errors that occur in a next-generation Intel Ita-
nium processor will be corrected by the hardware itself, without
any need for software intervention.
Conclusion
Intel Itanium processor 9500 series builds on the mainframe-
class capabilities delivered by previous-generation Intel Itanium
processor 9300 series. In addition to major improvements in
performance and throughput, it includes new, enhanced, and
extended RAS features to enable improved data integrity and
higher levels of system resiliency in mission-critical computing
environments.
A prime example of this enhanced RAS support is Intel Instruc-
tion Replay Technology, which automatically detects and cor-
rects soft errors in the instruction pipeline. With this technology,
soft errors can be identied and corrected in as few as seven
clock cycles, which is fast enough to be invisible to the software
running on the platform. Through this and many other improve-
ments throughout the platform, Intel Itanium processor 9500
series marks another signicant step forward in capability and
value for mission-critical computing.
For more information on Intel® Itanium® processor 9500 series,
visit www.intel.com/Itanium
Ratchet Up Reliability for Mission-Critical Applications
1
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