Applications paper

Figure 1 Poulson Replay Pipeline. Intel Itanium processor 9500 series feature
multiple replay paths for hazard avoidance and error correction.
A microprocessor pipeline is like the conveyor belt of an assembly line (Figure
1). It is divided into a number of stages. At each stage, a different step of the
process is performed. Once in the pipeline, the instructions from the software
program can act directly on data or other input. They can also direct data to be
moved among the memory, cache, and register hierarchy so the right data will
be available at the right time to enable efcient processing.
Each core in an Intel Itanium processor includes three main sections:
• The instruction fetch pipeline accesses main memory and brings needed
instructions into the processor’s caches. It also identifies the next set of in-
structions to execute and feeds them into the instruction buffer.
• The instruction execution pipeline reads and executes instructions from
the instruction buffer to perform operations on data, such as an addition or
multiplication.
• The data memory access pipeline brings needed data into the processor
caches from main memory and writes processed data back into memory as ap-
propriate, through the local data cache.
Replays—resolving resource hazards and correcting many soft errors
In some cases, an instruction moving through the pipeline encounters a “re-
source hazard” that prevents immediate execution. This happens when execu-
tion requires results or resources that are not yet available. Resource hazards
are detected in the pipeline and can be resolved by a replay.
In a replay, the instruction that encountered the resource hazard is removed
from the pipeline, along with all the instructions that come after it. The in-
struction is then read again out of the instruction buffer and restarted at the
beginning of the pipeline. All the instructions that follow it are also reread from
the buffer. To ensure a replay can be initiated for any instruction in the pipeline
that encounters a resource hazard, a copy of each instruction is maintained
FASTER PERFORMANCE FOR ENTERPRISE
WORKLOADS
The next-generation Intel® Itanium®
processor family provides a major leap in
performance for mission-critical work-
loads. It doubles the number of cores ver-
sus the Intel® Itanium® processor 9300
series (from four to eight) and imple-
ments a new 12-wide issue architecture
to reture up to twice the instructions
per cycle per core. With these and other
enhancements, it can provide dramatic
performance gains for existing code—
and even greater gains for software that
is recompiled to take advantage of the
new capabilities
Instruction
Buffer
IPG FET
FDC
REN
Back-End
Front-End
Replay Path
Replay Path
REG EXE DET WRB WB2DEC
IPG - Instruction Pointer Generate
FET - Instruction Fetch
FDC - Instruction Fetch Decode
REN - Register Rename
IBD - Instruction Buffer & Dispersal
DEC - Instruction Decode
REG - Register Access
EXE - Instruction Execute
DET - Detect Exceptions
WRB - Writeback, Commit Generate
WB2 - Writeback-2 Retire
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Ratchet Up Reliability for Mission-Critical Applications
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