Intel Core2 Extreme Processor X6800 and Intel Core2 Duo Desktop Processor E6000 and E4000 Sequences Datasheet

Datasheet 21
Electrical Specifications
V
CCPLL
PLL V
CC
- 5% 1.50 + 5%
I
CC
Processor Number
E6850
E6750
E6700
E6600
E6550
E6540
E6400/E6420
E6300/E6320
E4700
E4600
E4500
E4400
E4300
I
CC
for
775_VR_CONFIG_06
3.00 GHz
2.66 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.33 GHz
2.13 GHz
1.86 GHz
2.60 GHz
2.40 GHz
2.20 GHz
2.00 GHz
1.80 GHz
——
75
75
75
75
75
75
75
75
75
75
75
75
75
A
7
Processor Number
X6800
I
CC
for
775_VR_CONFIG_05B
2.93 GHz
——
90
V
TT
FSB termination voltage
(DC + AC specifications)
1.14 1.20 1.26 V
8
VTT_OUT_LEFT and
VTT_OUT_RIGHT I
CC
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per
pin
— — 580 mA
9
I
TT
I
CC
for V
TT
supply before V
CC
stable
I
CC
for V
TT
supply after V
CC
stable
——
4.5
4.6
A
10
I
CC_VCCPLL
I
CC
for PLL land — — 130 mA
I
CC_GTLREF
I
CC
for GTLREF — — 200 μA
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such
that two processors at the same frequency may have different settings within the VID range. Note this differs
from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
®
Technology, or Extended HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See Section 2.3 and Table 2 for more information.
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket
with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system
is not coupled into the oscilloscope probe.
6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum V
CC
allowed for a given current. The
processor should not be subjected to any V
CC
and I
CC
combination wherein V
CC
exceeds V
CC_MAX
for a given
current.
7. I
CC_MAX
specification is based on the V
CC_MAX
loadline. Refer to Figure 1 for details.
8. V
TT
must be provided via a separate voltage source and not be connected to V
CC
. This specification is measured
at the land.
9. Baseboard bandwidth is limited to 20 MHz.
10.This is maximum total current drawn from V
TT
plane by only the processor. This specification does not include
the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total I
TT
drawn by the
system. This parameter is based on design characterization and is not tested.
Table 5. Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Notes
1, 2