Intel Core2 Duo Processor E8000 and E7000 Series Specification Update

Errata
Intel
®
Core
™
2 Duo Processor
Specification Update – December 2010 47
with no virtual-NMI blocking but with blocking of events by either MOV SS or
STI, such a VM exit should occur after execution of one instruction in VMX
non-root operation. Due to this erratum, the VM exit may be delayed by one
additional instruction.
Implication: VMM software using “NMI-window exiting” for NMI virtualization should
generally be unaffected, as the erratum causes at most a one-instruction
delay in the injection of a virtual NMI, which is virtually asynchronous. The
erratum may affect VMMs relying on deterministic delivery of the affected VM
exits.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW79. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the
operand associated with the last non-control FP instruction executed by the
processor. If an 80-bit FP access (load or store) uses a 32-bit address size in
64-bit mode and the memory access wraps a 4-Gbyte boundary and the FP
environment is subsequently saved, the value contained in the FP Data
Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping
an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal
programming practice. Intel has not observed this erratum with any
commercially available software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which
may run code accessing 32-bit addresses, care must be taken to ensure that
no 80-bit FP accesses are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AW80. VM Entry May Overwrite the Value for the IA32_DEBUGCTL MSR
Specified in the VM-Entry MSR-Load Area
Problem: Following a successful VM entry with the “load debug controls” VM-entry
control set to 1, the IA32_DEBUGCTL MSR (1D9H) will always contain the
value held in the guest IA32_DEBUGCTL field in the virtual-machine control
structure (VMCS). If there is a value for the MSR in the VM-entry MSR-load
area, the processor will incorrectly overwrite that value with the value in the
VMCS.
Implication: Due to this erratum, VM entry may result in the wrong value being loaded
into the IA32_DEBUGCTL MSR. Intel has not observed this erratum with any
commercially available software.