Intel Core2 Duo Processor E8000 and E7000 Series Specification Update

Errata
Intel
®
Core
™
2 Duo Processor
Specification Update – December 2010 39
Implication: A VM Exit will occur when a VMX Abort was expected.
Workaround: An SMM VMM should always set the “IA-32e guest” VM-entry control in the
SMM VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit
10]) in the IA32_EFER MSR (C0000080H) at the time of the last SMM VM
exit. If this guideline is followed, that value will be 1 only if the “host
address-space size” VM-exit control is 1 in the executive VMCS.
Status: For the steppings affected, see the Summary Tables of Changes.
AW57. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on
the IRET instruction even though alignment checks were disabled at the start
of the IRET. This can only occur if the IRET instruction is returning from
CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum
can occur if the EFLAGS value on the stack has the AC flag set, and the
interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a
16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC
even if alignment checks are disabled at the start of the IRET. This erratum
can only be observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Tables of Changes.
AW58. PSI# Signal Asserted During Reset
Problem: Power Status Indicator (PSI) is a feature that, when available, may be used
to enable voltage regulator power savings while idle and in the Deeper Sleep
State (C4 state). Under proper operation the processor will assert the PSI#
signal to indicate that the voltage regulator can enter a higher efficiency
mode of operation. The processor will incorrectly assert the PSI# signal while
the RESET# signal is asserted. This PSI# assertion will extend beyond the
deassertion of the RESET# signal for a short duration (maximum of one
millisecond).
Implication: When this erratum occurs on a platform designed to support PSI, the voltage
regulator will transition to mode of operation that may not be capable of
supplying the necessary voltage and current required by the processor.
Workaround: Do not use PSI# signal without blocking the assertion during the error period
as specified from RESET# assertion to a maximum of 1ms from the
deasserted edge.
Status: For the steppings affected, see the Summary Tables of Changes.