Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 47
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first far JMP. Intel
®
64 and IA-32 Architectures Software
Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the far JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
§