Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process
Errata
44 Specification Update
AE75. Microcode Updates Performed During VMX Non-root Operation Could
Result in Unexpected Behavior
Problem: When Intel
®
Virtualization Technology is enabled, microcode updates are allowed only
during VMX root operations. Attempts to apply microcode updates while in VMX non-
root operation should be silently ignored. Due to this erratum, the processor may
allow microcode updates during VMX non-root operations if not explicitly prevented by
the host software.
Implication: Microcode updates performed in non-root operation may result in unexpected system
behavior.
Workaround: Host software should intercept and prevent loads to IA32_BIOS_UPDT_TRIG MSR
(79H) during VMX non-root operations. There are two mechanism that can be used (1)
Enabling MSR access protection in the VM-execution controls or (2) Enabling selective
MSR protection of IA32_BIOS_UPDT_TRIG MSR.
Status: For the steppings affected, see the Summary Tables of Changes.
AE76. INVLPG Operations for Large (2M/4M) Pages May Be Incomplete
under Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
(TLB) entries for large pages (2M/4M) when both of the following conditions exist:
Address range of the page being invalidated spans several Memory Type
Range Registers (MTRRs) with different memory types specified
INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page table Entry (PTE))
Implication: Stale Translations may remain valid in TLB after a PTE update resulting in
unpredictable system behavior. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for
the entire address range of the large page.
Status: For the steppings affected, see the Summary Tables of Changes.
AE77. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A Bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page, which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code
segment limit.