Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 43
AE72. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e., residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Please refer to “Procedure Calls For Block-Structured Languages” in the
IA-32 Intel
®
Architecture Software Developers Manual, Volume 1, Basic Architecture,
for information on the usage of ENTER instructions. This erratum is not expected to
occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when
transferring to ring 0. Intel has not observed this erratum on any commercially-
available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE73. Non-Temporal Data Store May Be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (i.e., later load operations may read
older data).
Implication: Software that uses non-temporal data without proper serialization before accessing
the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel
®
64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A, section “Buffering of Write Combining Memory Locations” will
operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AE74. Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
Problem: When an unaligned access is performed on paging structure entries, accessing a
portion of two different entries simultaneously, the processor may livelock.
Implication: When this erratum occurs, the processor may livelock causing a system hang.
Workaround: Do not perform unaligned access on paging structure entries.
Status: For the steppings affected, see the Summary Tables of Changes.