Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process
Errata
42 Specification Update
DR7 GD (General Detect, bit 13) being bit set
INT1 instruction
Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE69. BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software
interrupt may result in the overwriting of BTM/BTS branch-from instruction address by
the LBR (Last Branch Record) branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE70. Store to WT Memory Data May Be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get
the data from external memory or L2 written by another core, while the second load
will get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Workaround: Do not use WB to WT aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.
AE71. Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem: In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows
#DB is signaled before the pending higher priority #MF (Interrupt 16).
#DB is generated twice on the same instruction.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.