Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
34 Specification Update
AE45. Last Exception Record (LER) MSRs May Be Incorrectly Updated
Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect
values after the following events: masked SSE2 floating-point exception, StopClk, NMI
and INT.
Implication: The value of the LER MSR may be incorrectly updated to point to a SIMD Floating-
Point instruction even though no exception occurred on that instruction or to point to
an instruction that was preceded by a StopClk interrupt or rarely not to be updated on
Interrupts (NMI and INT).
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE46. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment
Selector” to SS and CS Registers
Problem: According to the processor specification, attempting to load a null segment selector
into the CS and SS segment registers should generate a General Protection Fault
(#GP). Although loading a null segment selector to the other segment registers is
allowed, the processor will generate an exception when the segment register holding a
null selector is used to access memory. However, the SYSENTER instruction can
implicitly load a null value to the SS segment selector. This can occur if the value in
SYSENTER_CS_MSR is between FFF8h and FFFBh when the SYSENTER instruction is
executed. This behavior is part of the SYSENTER/SYSEXIT instruction definition; the
content of the SYSTEM_CS_MSR is always incremented by 8 before it is loaded into
the SS. This operation will set the null bit in the segment selector if a null result is
generated, but it does not generate a #GP on the SYSENTER instruction itself. An
exception will be generated as expected when the SS register is used to access
memory, however. The SYSEXIT instruction will also exhibit this behavior for both CS
and SS when executed with the value in SYSENTER_CS_MSR between FFF0h and
FFF3h, or between FFE8h and FFEBh, inclusive.
Implication: These instructions are intended for operating system use. If this erratum occurs (and
the OS does not ensure that the processor never has a null segment selector in the SS
or CS segment registers), the processor‟s behavior may become unpredictable,
possibly resulting in system failure.
Workaround: Do not initialize the SYSTEM_CS_MSR with the values between FFF8h and FFFBh,
FFF0h and FFF3h, or FFE8h and FFEBh before executing SYSENTER or SYSEXIT.
Status: For the steppings affected, see the Summary Tables of Changes.