Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 29
AE31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after
Entry into SMM
Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction
following MOV SS/POP SS instructions. Immediately after executing these instructions,
if the processor enters SMM (System Management Mode), upon RSM (resume from
SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is
restored.
Because of this erratum, Data Breakpoints/Single step exceptions on MOVSS/POPSS
instructions may be lost under one of the following conditions:
1. Following SMM entry and after RSM, the next instruction to be executed is HLT
or MWAIT, or
2. SMM entry after executing MOV SS/POP SS is the result of executing an I/O
instruction that triggers a synchronous SMI (System Management Interrupt).
Implication: Data Breakpoints/Single step operation on MOV SS/POP SS instructions may be
unreliable in the presence of SMIs.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE32. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong
Address Onto the Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all
higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM
(Resume from System Management Mode) returns to execution flow that results in a
Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority Interrupt or Exception (e.g. NMI (Non-Maskable Interrupt), Debug
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a non-
canonical address, the address pushed onto the stack for this #GP fault may not
match the non-canonical address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commercially
available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE33. Hardware Prefetch Performance Monitoring Events May Be Counted
Inaccurately
Problem: Hardware prefetch activity is not accurately reflected in the hardware prefetch
performance monitoring.
Implication: This erratum may cause inaccurate counting for all hardware prefetch performance
monitoring events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.