Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
28 Specification Update
AE27. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4-G
limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur, the system may not issue a #GP fault.
Workaround: Software should ensure that memory accesses do not occur above the 4-G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AE28. Performance Monitoring Events for Retired Floating Point Operations
(C1h) May Not Be Accurate
Problem: Performance Monitoring Events that count retired floating point operations may be too
high.
Implication: The Performance Monitoring Event may have an inaccurate count.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE29. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFh)
Problem: Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of error is dependent on the number of occurrences
of the conditions described above, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE30. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM Instruction before Restoring the Architectural
State from SMRAM
Problem: Resume from System Management Mode (RSM) does not flush global pages from
DTLB before the System Management RAM (SMRAM) loads.
Implication: If SMM turns on paging with global paging enabled and then maps any of linear
addresses of SMRAM using global pages, RSM load may load data from the wrong
location.
Workaround: Do not use global pages in system management mode.
Status: For the steppings affected, see the Summary Tables of Changes.