Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 27
AE24. Disabling of Single-Step On-branch Operation May Be Delayed
following a POPFD Instruction
Problem: Disabling of Single-step On-branch Operation may be delayed, if the following
conditions are met:
1. “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF
are set).
2. POPFD used to clear EFLAGS.TF.
3. A jump instruction (JMP, Jcc, etc.) is executed immediately after POPFD.
Implication: Single-step On-branch mode may remain in effect for one instruction after the POPFD
instruction disables it by clearing the EFLAGS.TF bit.
Workaround: There is no workaround for Single-Step operation in commercially-available software.
The workaround for custom software is to execute at least one instruction following
POPFD before issuing a JMP instruction.
Status: For the steppings affected, see the Summary Tables of Changes.
AE25. Performance Monitoring Counters That Count External Bus Events May
Report Incorrect Values after Processor Power State Transitions
Problem: Performance monitoring counters that count external bus events operate when the
processor is in the Active state (C0). If a processor transitions to a new power state,
these Performance monitoring counters will stop counting, even if the event being
counted remains active.
Implication: After transitioning between processor power states, software may observe incorrect
counts in Performance monitoring counters that count external bus events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE26. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag
(ZF) is zero after executing the following instructions:
1. VERR (ZF=0 indicates unsuccessful segment read verification)
2. VERW (ZF=0 indicates unsuccessful segment write verification)
3. LAR (ZF=0 indicates unsuccessful access rights load)
4. LSL (ZF=0 indicates unsuccessful segment limit load)
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are
executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status: For the steppings affected, see the Summary Tables of Changes.