Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata

Specification Update 25

AE17. Machine Check Exception May Occur When Interleaving Code between

Different Memory Types

Problem: A small window of opportunity exists where code fetches interleaved between different

memory types may cause a machine check exception. A complex set of micro-

architectural boundary conditions is required to expose this window.

Implication: Interleaved instruction fetches between different memory types may result in a

machine check exception. The system may hang if machine check exceptions are

disabled. Intel has not observed the occurrence of this erratum while running

commercially-available applications or operating systems.

Workaround: Software can avoid this erratum by placing a serializing instruction between code

fetches between different memory types.

Status: For the steppings affected, see the Summary Tables of Changes.

AE18. Processor Digital Thermal Sensor (DTS) Readout Stops Updating upon

Returning from C3/C4 state

Problem: Digital Thermal Sensor (DTS) Readout is provided in IA32_THERM_STATUS bits 22:16.

Upon waking up from C3/C4 low-power state, the DTS readout will no longer be

updated.

Implication: Upon waking up from C3/C4 low-power state, software cannot rely on DTS readout

any thermal threshold interrupts that are enabled in IA32_THERM_INTERRUPT, will

also be affected.

Workaround: It is possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AE19. Data Prefetch Performance Monitoring Events Can Only Be Enabled on

a Single Core

Problem: Current implementation of Data Prefetch performance monitoring events allows

counting only for a single core at a time.

Implication: Dual-core support for counting Data Prefetch performance monitoring events is not

currently available.

Workaround: Software should enable Data Prefetch performance monitoring events on one core at a

time.

Status: For the steppings affected, see the Summary Tables of Changes.