Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
24 Specification Update
AE14. MOV to/from Debug Register Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AE15. INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register).
2. G bit for the page table entry is set.
3. TLB entry is present in TLB when INIT occurs.
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 or CR0 registers before writing to memory early in BIOS code to
clear all the global entries from TLB.
Status: For the steppings affected, see the Summary Tables of Changes.
AE16. Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
Problem: Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang or to report a Machine Check Exception (MCE). This would occur if one of the
addresses is non-cacheable used in code segment and the other a cacheable address.
If the cacheable address finds its way in instruction cache, and non-cacheable address
is fetched in IFU, the processor may invalidate the non-cacheable address from the
fetch unit. Any micro-architectural event that causes instruction restart will expect this
instruction to still be in fetch unit and lack of it will cause a system hang or an MCE.
Implication: This erratum has not been observed with commercially-available software.
Workaround: Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status: For the steppings affected, see the Summary Tables of Changes.