Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Summary Tables of Changes
Specification Update 15
Number
Stepping
Plans
ERRATA
C0
D0
Dual Core
Only
AE81
X
X
No Fix
Store Ordering May be Incorrect between WC and WP Memory
Types
AE82
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May
Not Count Some Transitions
AE83
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead
to Memory-Ordering Violations
AE84
X
X
No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
Number
SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision
Number
SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision
Number
DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision
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