Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 45
Status: For the steppings affected, see the Summary Tables of Changes.
AE78. Performance Monitoring Event for Hardware Prefetch Requests (4EH)
and Hardware Prefetch Request Cache Misses (4FH) May Not Be
Accurate
Problem: Performance monitoring event that count hardware prefetch requests and prefetch
misses may not be accurate.
Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and
Hardware Prefetch Request Cache Misses.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE79. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
Problem: When the processor is going into shutdown due to an RSM inconsistency failure,
EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be
asserted. This may be observed if the processor is taken out of shutdown by NMI#.
Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0
and CR4. In addition the EXF4 signal may still be asserted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE80. An Asynchronous MCE during a Far Transfer May Corrupt ESP
Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR
RET or IRET and in the presence of certain internal conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, e.g., when the CPL (Current
Privilege Level) was changed or when going through an interrupt task gate, then the
corrupted ESP will be saved on the new stack or in the TSS (Task State Segment), and
will not be used.
Workaround: Use an interrupt task gate for the machine check handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AE81. Store Ordering May be Incorrect between WC and WP Memory Types
Problem: According to IA-32 Intel
®
Architecture Software Developer's Manual, Volume 3A
"Methods of Caching Available", WP (Write Protected) stores should drain the WC
(Write Combining) buffers in the same way as UC (Uncacheable) memory type stores
do. Due to this erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.