Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 41
AE65. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may
result in unpredictable system behavior.
Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in
unpredictable system behavior. Intel has not observed this behavior in commercially-
available software.
Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
Status: For the steppings affected, see the Summary Tables of Changes.
AE66. A Thermal Interrupt Is Not Generated When the Current Temperature
Is Invalid
Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it
generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits
[9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated
IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of
the programmed thresholds is crossed and the corresponding log bits become set.
Implication: When the temperature reaches an invalid temperature the CPU does not generate a
Thermal interrupt even if a programmed threshold is crossed.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE67. Performance Monitoring Event FP_ASSIST May Not Be Accurate
Problem: Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist events
will be counted twice per actual assist in the following specific cases:
 FADD and FMUL instructions with a Not a Number (NaN) operand and a
memory operand
 FDIV instruction with zero-operand value in memory.
In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and
FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs.
Implication: The counter value for performance monitoring event FP_ASSIST (11H) may be larger
than expected. The size of the error is dependent on the number of occurrences of the
above condition while the event is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE68. The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8)
of the EFLAGS Register is set and a #DB (Debug Exception) occurs due to one of the
following: