Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 39
(IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may
contain incorrect data.
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return
incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE59. Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing
with the memory types WB and WT may cause the processor to perform incorrect
operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior. Intel chipset-based platforms are not affected by this erratum.
Workaround: None identified. Intel does not support the use of WB and WT page memory type
aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.
AE60. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the
sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without
having an invalid stack during interrupt handling. However, an enabled debug
breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is
followed by an instruction that signals a floating point exception rather than a MOV
[r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an
unexpected instruction boundary since the MOV SS/POP SS and the following
instruction should be executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV
[r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially available
software, or system.
Workaround: As recommended in the IA32 Intel
®
Architecture Software Developer‟s Manual, the use
of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since
the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of
debug tools should be aware of the potential incorrect debug event signaling created
by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AE61. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update