Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 37
Implication: There may be a smaller than expected value in the INST_RETIRED performance
monitoring counter. The extent to which this value is smaller than expected is
determined by the frequency of the above cases.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE52. #GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit Is Not Supported
Problem: #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor
which does not support Execute Disable Bit functionality.
Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE53. Update Of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB
shootdown (as defined by the 4 step procedure in "Propagation of Page Table and
Page Directory Entry Changes to Multiple Processors" In volume 3A of the IA-32 Intel
®
Architecture Software Developer's Manual), in conjunction with a complex sequence of
internal processor micro-architectural events, may lead to unexpected processor
behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior.
Intel has not observed this erratum with any commercially-available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AE54. SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event
may cause unexpected behavior. The SMC event occurs on a full address match of
code contained in L1 cache.
Implication: Due to this erratum, any of the following events may occur:
1. A data access break point may be incorrectly reported on the instruction
pointer (IP) just before the store instruction.
2. A non-cacheable store can appear twice on the external bus (the first time it
will write only 8 bytes, the second time it will write the entire 16 bytes).
Note: Intel has not observed this erratum with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.