Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process

Errata
Specification Update 35
AE47. Writing the Local Vector Table (LVT) When an Interrupt Is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AE48. Using 2-M/4-M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 MB. However, if all of the
following conditions are met, address bit 20 may not be masked:
 paging is enabled
 a linear address has bit 20 set
 the address references a large page
 A20M# is enabled.
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially-available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address
bit 20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status: For the steppings affected, see the Summary Tables of Changes.
AE49. Counter Enable Bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
Problem: According to the Architectural Performance Monitoring specification the two PerfMon
counters can be disabled/enabled through the corresponding Counter Enable bit [22]
of IA32_CR_PerfEvtSel0/1.
Due to this erratum, the following occurs:
1. bit [22] of IA32_CR_PerfEvtSel0 enables/disables both counters
2. bit [22] of IA32_CR_PerfEvtSel1 doesn't function